DF36034GFPJV Renesas Electronics America, DF36034GFPJV Datasheet - Page 374
![MCU 3/5V 32K J TEMP PB-FREE 64LQ](/photos/28/61/286100/64-lqfp__plqp0064kb-a_sml.jpg)
DF36034GFPJV
Manufacturer Part Number
DF36034GFPJV
Description
MCU 3/5V 32K J TEMP PB-FREE 64LQ
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Specifications of DF36034GFPJV
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 15 Controller Area Network for Tiny (TinyCAN)
15.5.5
A Mailbox can be reconfigured using the following procedure:
Changing CAN-ID and MBCR of Transmit Mailbox: Make sure that the bit corresponding to
the Mailbox in TXPR is not set to 1. The identifier of the transmit Mailbox and corresponding
MBCR bit can be changed at any time. If both of them need to be changed, change the identifier
first, clear RXPR and RFPR to 0, and then change MBCR.
Changing CAN-ID, MBCR, and LAFM of Receive Mailbox:
<Method 1: Halt mode (see figure 15.17)>
1. Set the HLTRQ bit in MCR bit to 1.
2. Determine whether the TinyCAN is during transmission or reception, or in the bus off state
3. The TinyCAN enters halt mode at the first bit in the intermission frame of the message and
4. Confirm that the RHI bit in TCIRR0 and the HALT bit in GSR are both set to 1 before
5. When the HLTRQ bit in MCR is cleared to 0, the TinyCAN returns to normal operation after
<Method 2: Other than halt mode (see figure 15.17)>
1. Set the MBn bit in MBIMR for the corresponding Mailbox to 1 to disable interrupts. (n = 0 to
2. Determine whether the MBn bits in RXPR and RFPR are cleared to 0 to confirm that there are
3. Change the settings of the identifier, LAFM, and the MBn bit in MBCR in the Mailbox.
4. Determine whether the MBn bits in RXPR and RFPR are cleared to 0 to confirm that no
5. At this time, when the MBn bit in RXPR or RFPR is set to 1, clear the relevant bit to 0. Delete
6. Then clear the MBn bit in MBIMR for the corresponding Mailbox to 0. The TinyCAN returns
Rev. 4.00 Mar. 15, 2006 Page 340 of 556
REJ09B0026-0400
and wait for recovery from transmission, reception, or bus off state.
sets the RHI bit in TCIRR0 and the HALT bit in GSR to 1. Note that the TinyCAN cannot
transmit or receive a message in halt mode.
changing settings of the identifier, LAFM, and the MBn bit in MBCR of the Mailbox.
11 recessive bits have been continuously received.
3)
no receive messages.
message is received during reconfiguration. The function of MBIMR is not to prevent RXPR,
RFPR, or the OVRI bit in TCIRR1 from being set.
the receive message because it cannot be determined whether the message was addressed to the
new Mailbox ID or the old Mailbox ID.
to normal operation.
Reconfiguring Mailbox
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