DF36034GFPJV Renesas Electronics America, DF36034GFPJV Datasheet - Page 405
![MCU 3/5V 32K J TEMP PB-FREE 64LQ](/photos/28/61/286100/64-lqfp__plqp0064kb-a_sml.jpg)
DF36034GFPJV
Manufacturer Part Number
DF36034GFPJV
Description
MCU 3/5V 32K J TEMP PB-FREE 64LQ
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Specifications of DF36034GFPJV
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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16.4.7
Figure 16.10 shows the initialization in four-line bus communication mode. Before transmitting
and receiving data, the TE and RE bits in SSER should be cleared to 0, then the SSU should be
initialized.
Note: When the operating mode, or transfer format, is changed for example, the TE and RE bits
must be cleared to 0 before making the change using the following procedure. When the
TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not
change the contents of the RDRF and ORER flags, or the contents of SSRDR.
Initialization in Four-Line Bus Communication Mode
[1]
[2]
Figure 16.10 Initialization in Four-Line Bus Communication Mode
according to transmission/reception/
Set TE and RE in SSER to 1 and
set RIE, TIE, TEIE, and RSSTP
Clear TE and RE in SSER to 0
set BIDE, MSS, SOOS, CSS1,
Set SCKS in SSCRH to 1 and
Set SSUMS in SSCRL to 1
Set MLS in SSMR to 1 and
transmission and reception
Clear ORER in SSSR to 0
set CPOS, CPHS, and
CKS2 to CKS0
and CSS0
Start
End
Section 16 Synchronous Serial Communication Unit (SSU)
[1] The MLS bit is set to 1 for MSB-first transfer.
[2] In bidirectional mode, the BIDE bit is set
The clock polarity and phase are set in the
CPOS and CPHS bits.
to 1 and input/output of the SCS pin is set
by the CSS1 and CSS0 bits.
Rev. 4.00 Mar. 15, 2006 Page 371 of 556
REJ09B0026-0400
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