DF36054FPJ Renesas Electronics America, DF36054FPJ Datasheet - Page 11

• Manufacturer Part Number: DF36054FPJ
• Description: MCU 3/5V 32K J-TEMP 64-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36054FPJ

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F36054FPJ; HD64F36054FPJ

Section 1 Overview................................................................................................1
1.1
1.2
1.3
1.4
Section 2 CPU........................................................................................................9
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Section 3 Exception Handling .............................................................................49
3.1
3.2
Features................................................................................................................................. 1
Internal Block Diagram......................................................................................................... 3
Pin Arrangement ................................................................................................................... 4
Pin Functions ........................................................................................................................ 5
Address Space and Memory Map ....................................................................................... 10
Register Configuration........................................................................................................ 14
2.2.1
2.2.2
2.2.3
Data Formats....................................................................................................................... 18
2.3.1
2.3.2
Instruction Set ..................................................................................................................... 21
2.4.1
2.4.2
Addressing Modes and Effective Address Calculation....................................................... 32
2.5.1
2.5.2
Basic Bus Cycle .................................................................................................................. 38
2.6.1
2.6.2
CPU States .......................................................................................................................... 40
Usage Notes ........................................................................................................................ 42
2.8.1
2.8.2
2.8.3
Exception Sources and Vector Address .............................................................................. 50
Register Descriptions.......................................................................................................... 52
3.2.1
3.2.2
3.2.3
General Registers................................................................................................ 15
Program Counter (PC) ........................................................................................ 16
Condition-Code Register (CCR)......................................................................... 16
General Register Data Formats ........................................................................... 18
Memory Data Formats ........................................................................................ 20
Table of Instructions Classified by Function ...................................................... 21
Basic Instruction Formats ................................................................................... 31
Addressing Modes .............................................................................................. 32
Effective Address Calculation ............................................................................ 36
Access to On-Chip Memory (RAM, ROM)........................................................ 38
On-Chip Peripheral Modules .............................................................................. 39
Notes on Data Access to Empty Areas ............................................................... 42
EEPMOV Instruction.......................................................................................... 42
Bit-Manipulation Instruction .............................................................................. 42
Interrupt Edge Select Register 1 (IEGR1) .......................................................... 52
Interrupt Edge Select Register 2 (IEGR2) .......................................................... 53
Interrupt Enable Register 1 (IENR1) .................................................................. 54
Contents
Rev. 4.00 Mar. 15, 2006 Page ix of xxxii