DF36054FPJ Renesas Electronics America, DF36054FPJ Datasheet - Page 285

• Manufacturer Part Number: DF36054FPJ
• Description: MCU 3/5V 32K J-TEMP 64-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36054FPJ

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F36054FPJ; HD64F36054FPJ

This LSI includes a serial communication interface 3 (SCI3), which has two independent
channels*
communication. In asynchronous mode, serial data communication can be carried out using
standard asynchronous communication chips such as a Universal Asynchronous
Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA). A
function is also provided for serial communication between processors (multiprocessor
communication function).
Table 14.1 shows the SCI3 channel configuration and figure 14.1 shows a block diagram of the
SCI3. Since pin functions are identical for each of the two channels (SCI3 and SCI3_2*
explanations are not given in this section.
Notes: 1. Only one channel is available in the H8/36037 Group.
14.1
Asynchronous mode
Choice of asynchronous or clocked synchronous serial communication mode
Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously.
Double-buffering is used in both the transmitter and the receiver, enabling continuous
transmission and continuous reception of serial data.
On-chip baud rate generator allows any bit rate to be selected
External clock or on-chip baud rate generator can be selected as a transfer clock source.
Six interrupt sources
Transmit-end, transmit-data-empty, receive-data-full, overrun error, framing error, and parity
error.
Data length: 7 or 8 bits
Stop bit length: 1 or 2 bits
Parity: Even, odd, or none
Receive error detection: Parity, overrun, and framing errors
Section 14 Serial Communication Interface 3 (SCI3)
2. The H8/36037 Group does not have the SCI3_2.
1
Features
. The SCI3 can handle both asynchronous and clocked synchronous serial
Section 14 Serial Communication Interface 3 (SCI3)
Rev. 4.00 Mar. 15, 2006 Page 251 of 556
REJ09B0026-0400
2
), separate