DF36054FPJ Renesas Electronics America, DF36054FPJ Datasheet - Page 78

• Manufacturer Part Number: DF36054FPJ
• Description: MCU 3/5V 32K J-TEMP 64-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36054FPJ

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F36054FPJ; HD64F36054FPJ

Section 2 CPU
1. When the BSET instruction is executed, first the CPU reads port 5.
2. Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41.
3. Finally, the CPU writes H'41 to PDR5, completing execution of BSET instruction.
As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal.
However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a copy
of the PDR5 data in a work area in memory. Perform the bit manipulation on the data in the work
area, then write this data to PDR5.
Rev. 4.00 Mar. 15, 2006 Page 44 of 556
REJ09B0026-0400
Input/output
Pin state
PCR5
PDR5
Input/output
Pin state
PCR5
PDR5
RAM0
MOV.B
MOV.B
MOV.B
After executing BSET instruction
Description on operation
Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level
input).
P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a
value of H'80, but the value read by the CPU is H'40.
Prior to executing BSET instruction
#80,
R0L,
R0L,
P57
Input
Low
level
0
0
P57
Input
Low
level
0
1
1
R0L
@RAM0
@PDR5
P56
Input
High
level
0
1
P56
Input
High
level
0
0
0
P55
Output
Low
level
1
0
P55
Output
Low
level
1
0
0
The PDR5 value (H'80) is written to a work area in
memory (RAM0) as well as to PDR5.
P54
Output
Low
level
1
0
P54
Output
Low
level
1
0
0
P53
Output
Low
level
1
0
P53
Output
Low
level
1
0
0
P52
Output
Low
level
1
0
P52
Output
Low
level
1
0
0
P51
Output
1
P51
Output
1
0
0
Low
level
0
Low
level
P50
Output
High
level
1
1
P50
Output
Low
level
1
0
0