DF36054FPJ Renesas Electronics America, DF36054FPJ Datasheet - Page 305

• Manufacturer Part Number: DF36054FPJ
• Description: MCU 3/5V 32K J-TEMP 64-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36054FPJ

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F36054FPJ; HD64F36054FPJ

14.4.2
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR3 to 0,
then initialize the SCI3 as described below. When the operating mode, or transfer format, is
changed for example, the TE and RE bits must be cleared to 0 before making the change using the
following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing
the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and OER flags, or the
contents of RDR. When the external clock is used in asynchronous mode, the clock must be
supplied even during initialization.
SCI3 Initialization
and MPIE bits. For transmit (TE=1),
SCR3 to 1, and set RIE, TIE, TEIE,
Clear TE and RE bits in SCR3 to 0
Set CKE1 and CKE0 bits in SCR3
Set data transfer format in SMR
also set the TxD bit in PMR1.
<Initialization completion>
1-bit interval elapsed?
Set TE and RE bits in
Set value in BRR
Start initialization
Figure 14.4 Sample SCI3 Initialization Flowchart
Yes
Wait
No
[1]
[2]
[3]
[4]
Section 14 Serial Communication Interface 3 (SCI3)
[1]
[2]
[3]
[4]
Set the clock selection in SCR3.
Be sure to clear bits RIE, TIE, TEIE, and
MPIE, and bits TE and RE, to 0.
When the clock output is selected in
asynchronous mode, clock is output
immediately after CKE1 and CKE0
settings are made. When the clock
output is selected at reception in clocked
synchronous mode, clock is output
immediately after CKE1, CKE0, and RE
are set to 1.
Set the data transfer format in SMR.
Write a value corresponding to the bit
rate to BRR. Not necessary if an
external clock is used.
Wait at least one bit interval, then set the
TE bit or RE bit in SCR3 to 1. RE
settings enable the RXD pin to be used.
For transmission, set the TXD bit in
PMR1 to 1 to enable the TXD output pin
to be used. Also set the RIE, TIE, TEIE,
and MPIE bits, depending on whether
interrupts are required. In asynchronous
mode, the bits are marked at
transmission and idled at reception to
wait for the start bit.
Rev. 4.00 Mar. 15, 2006 Page 271 of 556
REJ09B0026-0400