M30800SFP-BL#D5 Renesas Electronics America, M30800SFP-BL#D5 Datasheet - Page 170

• Manufacturer Part Number: M30800SFP-BL#D5
• Description: MCU 3/5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#D5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
1
v
J
6
Figure 20.2 Functional block diagram for I
1 .
0
C
9
0 .
8 /
P7
B
P7
Figure 20.2 is a block diagram of the IIC bus interface.
To explain the control bit of the IIC bus interface, UART2 is used as an example.
P7
0
0
UART2 Special Mode Register (Address 0337
0
0
1
/TXD
1
2
/RXD
/CLK
A
Bit 0 is the IIC mode select bit. When set to “1”, ports P7
SDA2 data transmission-reception pin, SCL2 clock I/O pin and port P7
SDA2 transmission output, therefore after SCL2 is sufficiently L level, SDA2 output changes. Port P7
(SCL2) is designed to read pin level regardless of the content of the port direction register. SDA2
transmission output is initially set to port P7
collision detection interrupt, UART2 transmission interrupt and UART2 reception interrupt change
respectively to the start/stop condition detection interrupts, acknowledge non-detection interrupt and
acknowledge detection interrupt.
G
8
u
7
o r
2
. g
0 -
/SDA
2
2
/SCL
u
1
0
p
0
, 2
0
2
0
0
5
Page 157
Noize
Filter
Noize
Filter
Noize
Filter
Selector
Serector
Selector
UART2
f o
Falling edge
detection
3
2
IICM=1
IICM=0
Timer
I/O
9
IICM=1
IICM=0
UART2
UART2
Stop condition detection
Start condition detection
D
I/0
T
SDHI
Q
IICM=1
IICM=0
Timer
I/0
L-synchronous
output enabling bit
IICM=1
IICM=0
ALS
R
Arbitration
delay
2
C mode
Data register
Internal clock
External clock
* With IICM set to 1, the port terminal is to be readable
Port reading
0
even if 1 is assigned to P7
in this mode. Furthermore, interrupt factors for the bus
SWC2
R
S
16
Transmission register
)
20. UARTi Special Mode Register (i = 2 to 4)
S
R
CLK
control
UART2
Reception register
Q
Falling edge of 9th pulse
Bus
busy
UART2
UART2
0
, P7
SWC
Bus collision
detection
9th pulse
1
1
of the direction register.
D
D
T
T
and P7
Q
Q
IICM=0 or
IICM2=1
IICM=0 or IICM2=1
ACK
IICM=1 and
IICM2=0
IICM=1 and
IICM2=0
2
2
IICM=1
IICM=0
NACK
. A delay circuit is added to
operate respectively as the
Bus collision/start, stop
condition detection
interrupt request
UART2 reception/ACK
interrupt request
DMAi request
UART2
transmission/NACK
interrupt request
To DMAi
To DMAi
1