M30800SFP-BL#D5 Renesas Electronics America, M30800SFP-BL#D5 Datasheet - Page 27

• Manufacturer Part Number: M30800SFP-BL#D5
• Description: MCU 3/5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#D5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
1
v
J
6
1 .
0
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, R3, R2R0 and R3R1)
(2) Address registers (A0 and A1)
(3) Static base register (SB)
(4) Frame base register (FB)
(5) Program counter (PC)
(6) Interrupt table register (INTB)
(7) User stack pointer (USP), interrupt stack pointer (ISP)
(8) Save flag register (SVF)
C
9
0 .
8 /
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H),
and low-order bits as (R0L/R1L). Registers R2 and R0, as well as R3 and R1 can use as 32-bit data
registers (R2R0/R3R1).
Address registers (A0 and A1) are configured with 24 bits, and have functions equivalent to those of data
registers. These registers can also be used for address register indirect addressing and address register
relative addressing.
Static base register (SB) is configured with 24 bits, and is used for SB relative addressing.
Frame base register (FB) is configured with 24 bits, and is used for FB relative addressing.
Program counter (PC) is configured with 24 bits, indicating the address of an instruction to be executed.
Interrupt table register (INTB) is configured with 24 bits, indicating the start address of an interrupt vector
table.
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config-
ured with 24 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
Set USP and ISP to an even number so that execution efficiency is increased.
This register consists of 16 bits and is used to save the flag register when a high-speed interrupt is
generated.
B
0
0
0
1
A
8
G
u
7
o r
. g
0 -
u
1
0
p
0
, 2
0
2
0
0
5
Page 14
f o
3
2
9
3. Central Processing Unit (CPU)