M30800SFP-BL#D5 Renesas Electronics America, M30800SFP-BL#D5 Datasheet - Page 93

• Manufacturer Part Number: M30800SFP-BL#D5
• Description: MCU 3/5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#D5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
11. DMAC
e
E
1
v
J
6
Figure 11.1 Register map using DMAC
1 .
0
C
This microcomputer has four DMAC (direct memory access controller) channels that allow data to be sent
to memory without using the CPU. DMAC is a function that to transmit 1 data of a source address (8 bits /
16 bits) to a destination address when transmission request occurs. When using three or more DMAC
channels, the register bank 1 register and high-speed interrupt register are used as DMAC registers. If you
are using three or more DMAC channels, you cannot, therefore, use high-speed interrupts. The CPU and
DMAC use the same data bus, but the DMAC has a higher bus access privilege than the CPU, and because
of the use of cycle-steeling, operations are performed at high-speed from the occurrence of a transfer
request until one word (16 bits) or 1 byte (8 bits) of data have been sent. Figure 11.1 shows the mapping of
registers used by the DMAC. Table 11.1 shows DMAC specifications. Figures 11.2 to 11.5 show the
structures of the registers used.
As the registers shown in Figure 11.1 is allocated in CPU, use LDC instruction when writing. When writing
to DCT2, DCT3, DRC2, DRC3, DMA2 and DMA3, set register bank select flag (B flag) to "1" and use MOV
instruction to set R0 to R3, A0 and A1 registers. When writing to DSA2 and DSA3, set register bank select
flag (B flag) to "1" and use LDC instruction to set SB and FB registers.
In addition to writing to the software DMA request bit to start DMAC transfer, the interrupt request signals
output from the functions specified in the DMA request factor select bits are also used. However, in contrast
to the interrupt requests, repeated DMA requests can be received, regardless of the interrupt flag.
(Note, however, that the number of actual transfers may not match the number of transfer requests if the
DMA request cycle is shorter than the DMR transfer cycle. For details, see the description of the DMAC
request bit.)
9
0 .
8 /
B
When using three or more DMAC channels
The register bank 1 is used as a DMAC register
DMAC related register
0
0
0
1
A
8
G
u
7
o r
. g
0 -
u
DMA2 (A0)
DMA3 (A1)
DSA3 (FB)
1
DSA2 (SB)
0
p
0
, 2
0
DSA0
DSA1
DRA0
DRA1
DMA0
DMA1
DCT2 (R0)
DCT3 (R1)
DRC2 (R2)
DRC3 (R3)
2
0
DCT0
DCT1
DRC0
DRC1
0
5
DMD0
DMD1
Page 80
DMA3 transfer count register
DMA2 transfer count reload register
DMA3 transfer count reload register
DMA2 memory address register
DMA2 SFR address register
DMA2 transfer count register
DMA3 memory address register
DMA3 SFR address register
DMA0, 1 memory address register
DMA0, 1 SFR address register
DMA mode register 0, 1
DMA0, 1 transfer count register
DMA0,1 transfer count reload register
DMA0, 1 memory address reload register
f o
3
2
9
When using three or more DMAC channels
The high-speed interrupt register is used as a DMAC
register
When using DMA2 and DMA3, use the CPU
registers shown in parentheses.
DRA2 (SVP)
DRA1 (VCT)
SVF
Flag save register
DMA2 memory address reload register
DMA3 memory address reload register
11. DMAC