M30800SFP-BL#D5 Renesas Electronics America, M30800SFP-BL#D5 Datasheet - Page 83

• Manufacturer Part Number: M30800SFP-BL#D5
• Description: MCU 3/5V 0K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/80r

Specifications of M30800SFP-BL#D5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

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Figure 9.8 Interrupt resolution circuit
6
1 .
0
Low
C
High
9
Priority of peripheral I/O interrupts
(if priority levels are same)
0 .
8 /
B
0
0
0
1
A
8
G
Priority level of each interrupt
u
7
o r
. g
0 -
UART0 transmission
UART1 transmission
u
UART0 reception
UART1 reception
1
0
p
0
, 2
0
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
DMA0
DMA1
DMA2
DMA3
2
INT5
INT4
INT3
INT2
0
0
5
Page 70
Level 0 (initial value)
f o
3
2
9
Processor interrupt priority level
Stop/wait return interrupt level
condition/fault error (UART3)
condition/fault error (UART4)
UART4 transmission/NACK
UART2 transmission/NACK
UART3 transmission/NACK
Interrupt enable flag (I flag)
Bus collision/start, stop
Bus collision/start, stop
Bus collision/start, stop
UART2 reception/ACK
UART3 reception/ACK
UART4 reception/ACK
Key input interrupt
condition(UART2)
A/D conversion
Instruction fetch
Watchdog timer
Address match
Timer B5
(RLVL)
INT0
INT1
Reset
(IPL)
DBC
NMI
9. Interrupt Outline
Interrupt request priority
detection results output
(to clock generation circuit)
Interrupt
request
accepted.
To CPU