MC68HC11K0CFUE4 Freescale Semiconductor, MC68HC11K0CFUE4 Datasheet - Page 116

• Manufacturer Part Number: MC68HC11K0CFUE4
• Description: MCU 8-BIT 768 RAM 4MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11K0CFUE4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Resets and Interrupts
Technical Data
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– All nine timer interrupts are disabled because their mask bits
– The I4/O5 bit in the PACTL register is cleared to configure the
Real-time interrupt (RTI)
– The RTI enable bit in TMSK2 is cleared, masking automatic
– The rate control bits are cleared after reset and can be
Pulse accumulator
– The pulse accumulator system is disabled at reset.
– The PAI input pin defaults to a general-purpose input pin
Computer operating properly (COP) watchdog system
– The COP watchdog system is enabled if the NOCOP control
– The OPTION register’s CR[1:0] bits are cleared, setting the
Serial communications interface (SCI)
– At reset, the SCI baud rate control register
– All transmit and receive interrupts are masked and both the
– The SCI frame format is initialized to an 8-bit character size.
– The send break and receiver wake-up functions are disabled.
– The TDRE and TC status bits in the SCI status register are
have been cleared.
I4/O5 function as OC5; however, the OM5:OL5 control bits in
the TCTL1 register are clear so OC5 does not control the PA3
pin.
hardware interrupts.
initialized by software before the RTI system is enabled.
(PA7).
bit in the CONFIG register is clear and disabled if NOCOP is
set.
COP rate for the shortest duration timeout.
Rate Control
transmitter and receiver are disabled so the port pins default to
being general-purpose I/O lines.
both set, indicating that there is no transmit data in either the
transmit data register or the transmit serial shift register.
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Resets and Interrupts
Register) is initialized to $0004.
(7.9.1 SCI Baud
M68HC11K Family
MOTOROLA