MCF5280CVF66J Freescale Semiconductor, MCF5280CVF66J Datasheet - Page 16
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MCF5280CVF66J
Manufacturer Part Number
MCF5280CVF66J
Description
IC MPU RISC 66MHZ 256-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5280CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5280CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 16 of 766
- Download datasheet (9Mb)
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
17.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
17.3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
17.4 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
17.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-25
xvi
17.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
17.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
17.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.2.1 Full and Half Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
17.2.2 Interface Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
17.2.3 Address Recognition Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
17.2.4 Internal Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
17.4.1 MIB Block Counters Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7
17.4.2 Ethernet Interrupt Event Register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9
17.4.3 Interrupt Mask Register (EIMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10
17.4.4 Receive Descriptor Active Register (RDAR) . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
17.4.5 Transmit Descriptor Active Register (TDAR) . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
17.4.6 Ethernet Control Register (ECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
17.4.7 MII Management Frame Register (MMFR) . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13
17.4.8 MII Speed Control Register (MSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15
17.4.9 MIB Control Register (MIBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16
17.4.10Receive Control Register (RCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16
17.4.11Transmit Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17
17.4.12Physical Address Lower Register (PALR) . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18
17.4.13Physical Address Upper Register (PAUR) . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19
17.4.14Opcode/Pause Duration Register (OPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19
17.4.15Descriptor Individual Upper Address Register (IAUR) . . . . . . . . . . . . . . . . . 17-20
17.4.16Descriptor Individual Lower Address Register (IALR) . . . . . . . . . . . . . . . . . 17-20
17.4.17Descriptor Group Upper Address Register (GAUR) . . . . . . . . . . . . . . . . . . 17-21
17.4.18Descriptor Group Lower Address Register (GALR) . . . . . . . . . . . . . . . . . . . 17-21
17.4.19Transmit FIFO Watermark Register (TFWR) . . . . . . . . . . . . . . . . . . . . . . . . 17-22
17.4.20FIFO Receive Bound Register (FRBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-22
17.4.21FIFO Receive Start Register (FRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-23
17.4.22Receive Descriptor Ring Start Register (ERDSR) . . . . . . . . . . . . . . . . . . . . 17-23
17.4.23Transmit Buffer Descriptor Ring Start Registers (ETSDR) . . . . . . . . . . . . . 17-24
17.4.24Receive Buffer Size Register (EMRBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-24
17.5.1 Buffer Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-25
17.5.2 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-30
17.2.2.1 10 Mbps and 100 Mbps MII Interface . . . . . . . . . . . . . . . . . . . . . . . . 17-4
17.2.2.2 10 Mpbs 7-Wire Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
17.5.1.1 Driver/DMA Operation with Buffer Descriptors . . . . . . . . . . . . . . . . 17-25
17.5.1.2 Ethernet Receive Buffer Descriptor (RxBD) . . . . . . . . . . . . . . . . . . 17-27
17.5.1.3 Ethernet Transmit Buffer Descriptor (TxBD) . . . . . . . . . . . . . . . . . . 17-29
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Fast Ethernet Controller (FEC)
Chapter 17
Freescale Semiconductor
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