MCF5280CVF66J Freescale Semiconductor, MCF5280CVF66J Datasheet - Page 556
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MCF5280CVF66J
Manufacturer Part Number
MCF5280CVF66J
Description
IC MPU RISC 66MHZ 256-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5280CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5280CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Queued Analog-to-Digital Converter (QADC)
Once PFn is set, the queue enters the paused state and waits for a trigger event to allow queue execution
to continue. However, a special case occurs when the CCW with the pause bit set is the last CCW in a
queue; queue execution is complete. The queue status becomes idle, not paused, and both the pause and
completion flags are set.
Another special case occurs when the queue is operating in software-initiated single-scan or
continuous-scan mode and a CCW pause bit is set. The QADC will set PFn and will also automatically
generate a retrigger event that restarts execution after two QCLK cycles. Pause mode is never entered.
In externally gated single-scan and continuous-scan mode, the behavior of PFn has been redefined. When
the gate closes before the end of the queue is reached, PFn is set to indicate that an incomplete scan has
occurred. In single-scan mode, a resultant interrupt can be used to determine if the queue should be enabled
again. In either externally gated mode, setting PFn indicates that the results for the queue have not been
collected during one scan (coherently).
A trigger event generated by a transition on the external trigger signal or by the periodic/interval timer may
be captured as a trigger overrun. TORn cannot be set when the software-initiated single-scan mode or the
software-initiated continuous-scan mode is selected.
TORn is set when a trigger event is received while a queue is executing and before the scan has completed
or paused. TORn has no effect on queue execution.
After a trigger event has occurred for queue 1, and before the scan has completed or paused, additional
queue 1 trigger events are not retained. Such trigger events are considered unexpected, and the QADC sets
the TORn error status bit. An unexpected trigger event may denote a system overrun situation.
In externally gated continuous-scan mode, the behavior of TORn has been redefined. In the case that the
queue reaches an end-of-queue condition for the second time during an open gate, TORn is set. This is
considered an overrun condition. In this case, CF1 has been set for the first end-of-queue condition and
TORn sets for the second end-of-queue condition. For TOR1 to set, CF2 must not be cleared before the
second end-of-queue.
The QS field indicates the status of queue 1 and queue 2. Following are the five queue status conditions:
The idle state occurs when a queue is disabled, when a queue is in a reserved mode, or when a queue is in
a valid queue operating mode awaiting a trigger event to initiate queue execution. One or both queues may
be in the idle state. When a queue is idle, CCWs are not being executed for that queue, the queue is not in
the pause state, and no trigger is pending.
28-18
•
•
•
•
•
•
When the currently completed CCW is in the last location of the CCW RAM.
Idle
Active
Paused
Suspended
Trigger pending
If a set CCW pause bit is encountered in either externally gated mode, the
pause flag will not set, and execution continues without pausing. This has
allowed for the modified behavior of PF1 in the externally gated modes.
PFn is maintained by the QADC regardless of whether the corresponding
interrupt is enabled. PFn may be polled to determine if the QADC has
reached a pause in scanning a queue.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
NOTE:
Freescale Semiconductor
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