MCF5280CVF66J Freescale Semiconductor, MCF5280CVF66J Datasheet - Page 245
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MCF5280CVF66J
Manufacturer Part Number
MCF5280CVF66J
Description
IC MPU RISC 66MHZ 256-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5280CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5280CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Freescale Semiconductor
Receive data valid
Receive data 0
Carrier receive sense
Transmit data
Transmit error
Receive data
Receive error
QSPI synchronous
serial data output
QSPI synchronous
serial data input
QSPI serial clock
QSPI chip selects
FlexCAN transmit
FlexCAN transmit
Serial clock
Serial data
Transmit serial
data output
Receive serial
data input
Signal Name
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 14-1. MCF5282 Signal Description (continued)
ERXDV
ERXD0
ECRS
ETXD[3:1]
ETXER
ERXD[3:1]
ERXER
QSPI_DOUT
QSPI_DIN
QSPI_CLK
QSPI_CS[3:0]
CANTX
CANRX
SCL
SDA
UTXD[2:0]
URXD[2:0]
Queued Serial Peripheral Interface (QSPI) Signals
Abbreviation
FlexCAN Signals
UART Signals
Asserted to indicate that the PHY has
valid nibbles present on the MII.
Ethernet input data transferred from
the PHY to the media access controller
(when ERXDV is asserted).
or receive medium is not idle.
Contain the serial output Ethernet
data.
Asserted (for one or more E_TXCLKs
while ETXEN is also asserted) to
cause the PHY to send one or more
illegal symbols.
Contain the Ethernet input data
transferred from the PHY to the media
access controller (when ERXDV is
asserted in MII mode).
Indicates (when asserted with
ERXDV) that the PHY has detected an
error in the current frame.
Provides serial data from the QSPI.
Provides serial data to the QSPI.
Provides the serial clock from the
QSPI.
Provide QSPI peripheral chip selects.
Controller area network transmit data.
Transmitter serial data outputs.
Receiver serial data inputs.
Asserted to indicate that the transmit
Controller area network transmit data.
Clock signal for the I
Data input/output for the I
I
2
C Signals
Function
2
C interface.
2
C interface.
I/O
I/O
I/O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
Signal Descriptions
14-24
14-24
14-24
14-24
14-24
14-24
14-25
14-25
14-25
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14-25
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14-5
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