MCF5280CVF66J Freescale Semiconductor, MCF5280CVF66J Datasheet - Page 576
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MCF5280CVF66J
Manufacturer Part Number
MCF5280CVF66J
Description
IC MPU RISC 66MHZ 256-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5280CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5280CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Queued Analog-to-Digital Converter (QADC)
The first three examples in
a new trigger event is recognized before the queue has completed servicing the previous trigger event on
the same queue.
In situation S1
working on the previously recognized trigger event. The trigger overrun error status bit is set, and the
premature trigger event is otherwise ignored. A trigger event that occurs before the servicing of the
previous trigger event is through does not disturb the queue execution in progress.
In situation S2
trigger event is complete. The trigger overrun bit is again set, but the additional trigger events are otherwise
ignored. After the queue is complete, the first newly detected trigger event causes queue execution to begin
again. When the trigger event rate is high, a new trigger event can be seen very soon after completion of
the previous queue, leaving little time to retrieve the previous results. Also, when trigger events are
occurring at a high rate for queue 1, the lower priority queue 2 channels may not get serviced at all.
Situation S3
is set the same way and that queue execution continues unchanged.
28-38
QS:
Q1:
Q2:
QS:
Q1:
Q2:
IDLE
(Figure
Q1:
(Figure
T1
(Figure
C1
TOR1
T1
IDLE
28-25) shows that when the pause feature is used, the trigger overrun error status bit
0000
C2
28-23), one trigger event is being recognized on each queue while that queue is still
TOR1
ACTIVE
28-24), more than one trigger event is recognized before servicing of a previous
T1
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
1000
Figure 28-23
C3
TOR1
T1
Q1:
C4
T1
Figure 28-23. CCW Priority Situation 1
Figure 28-24. CCW Priority Situation 2
CF1
IDLE
IDLE
C1
IDLE
TOR1
T1
T1
C2
ACTIVE
through
C1
1000
C3
C2
ACTIVE
1000
Figure 28-25
C4
C3
CF1
C4
0000
CF1
Q2:
T2
(S1, S2, and S3) show what happens when
C1
0000
C2
ACTIVE
Q2:
TOR2
T2
0010
T2
C3
IDLE
IDLE
C1
C4
TOR2
T2
C2
ACTIVE
CF2
0010
TOR2
Freescale Semiconductor
C3
T2
IDLE
0000
C4
CF2
IDLE
0000
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