MCF5216CVF66J Freescale Semiconductor, MCF5216CVF66J Datasheet - Page 149
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MCF5216CVF66J
Manufacturer Part Number
MCF5216CVF66J
Description
IC MCU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF521xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5216CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
142
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF521x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
M52210DEMO, M52211EVB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5216CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 149 of 766
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7.3.2.24 ColdFire Flash Module
The ColdFire Flash Control Module is capable of generating interrupts by the setting of the CBEIF or
CCIF bits in the CFMUSTAT. These interrupt sources, however, should not occur when the device is in a
low-power mode as long as no Flash operation was in progress when the low-power mode was entered.
When performing a program or erase operation on the Flash, if a command is active (CCIF = 0) when the
MCU enters a low-power mode, the command sequence monitor will perform the following:
7.3.2.25 BDM
Entering halt mode via the BDM port (by asserting the external BKPT pin) will cause the CPU to exit any
low-power mode.
7.3.2.26 JTAG
The JTAG (Joint Test Action Group) controller logic is clocked using the TCLK input and is not affected
by the system clock. The JTAG cannot generate an event to cause the CPU to exit any low-power mode.
Toggling TCLK during any low-power mode will increase the system current consumption.
7.3.3
The functionality of each of the peripherals and CPU during the various low-power modes is summarized
in
automatically assumes when the STOP instruction is executed and the LPCR[LPMD] field is set for the
particular low-power mode. Individual peripherals may be disabled by programming its dedicated control
bits. The wakeup capability field refers to the ability of an interrupt or reset by that peripheral to force the
CPU into run mode.
Freescale Semiconductor
Table
•
•
1. The command in progress will be aborted.
2. The Flash high voltage circuitry will be switched off and any pending command (CBEIF = 0) will
3. The CCIF and ACCERR flags will be set if a command is active when the MCU enters
No host access to the FlexCAN module.
The FlexCAN is neither in halt mode (MCR bit 8), in stop mode (MCT bit 15), nor in BUSOFF.
not be executed when the MCU exits low-power mode.
low-power mode.
7-7. The status of each peripheral during a given mode refers to the condition the peripheral
Summary of Peripheral State During Low-Power Modes
The state of any longword(s) being programmed, or any erase
pages/physical blocks being erased, is not guaranteed if the MCU enters
stop mode with a command in progress. Active commands are immediately
aborted when the MCU enters stop mode. Do not execute the STOP
instruction during program and erase operations.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
NOTE
Power Management
7-13
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