MCF5216CVF66J Freescale Semiconductor, MCF5216CVF66J Datasheet - Page 587
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MCF5216CVF66J
Manufacturer Part Number
MCF5216CVF66J
Description
IC MCU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF521xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5216CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
142
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF521x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
M52210DEMO, M52211EVB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5216CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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bit should be cleared before another scan of queue 1 is initiated during the next open gate. The start of
queue 1 is always the first CCW in the CCW table.
Because the gate level is only sampled after each conversion during queue execution, closing the gate for
a period less than a conversion time interval does not guarantee the closure will be captured.
28.8.6.4 Interval Timer Single-Scan Mode
Both queues can use the periodic/interval timer in a single-scan queue operating mode. The timer interval
can range from 2
selected and the single-scan enable bit is set in QACR1 or QACR2, the timer begins counting. When the
time interval elapses, an internal trigger event is generated to start the queue and the QADC begins
execution with the first CCW.
The QADC automatically performs the conversions in the queue until a pause or an end-of-queue
condition is encountered. When a pause occurs, queue execution stops until the timer interval elapses
again, and queue execution continues. When queue execution reaches an end-of-queue situation, the
single-scan enable bit is cleared. Set the single-scan enable bit again to allow another scan of the queue to
be initiated by the interval timer.
The interval timer generates a trigger event whenever the time interval elapses. The trigger event may
cause queue execution to continue following a pause or may be considered a trigger overrun. Once queue
execution is completed, the single-scan enable bit must be set again to allow the timer to count again.
Normally, only one queue is enabled for interval timer single-scan mode, and the timer will reset at the
end-of-queue. However, if both queues are enabled for either single-scan or continuous interval timer
mode, the end-of-queue condition will not reset the timer while the other queue is active. In this case, the
timer will reset when both queues have reached end-of-queue. See
Timer
The interval timer single-scan mode can be used in applications that need coherent results. For example:
28.8.7
A continuous-scan queue operating mode is used to execute multiple passes through a sequence of
conversions defined by a queue. By programming the MQ1 field in QACR1 or the MQ2 field in QACR2,
these modes can be selected:
When a queue is programmed for a continuous-scan mode, the single-scan enable bit in the queue control
register does not have any meaning or effect. As soon as the queue operating mode is programmed, the
selected trigger event can initiate queue execution.
Freescale Semiconductor
•
•
•
•
•
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for a definition of interval timer reset conditions.
When it is necessary that all samples are guaranteed to be taken during the same scan of the analog
signals
When the interrupt rate in the periodic timer continuous-scan mode would be too high
In sensitive battery applications, where the interval timer single-scan mode uses less power than
the software-initiated continuous-scan mode
Software-initiated continuous-scan mode
Externally triggered continuous-scan mode
Externally gated continuous-scan mode
Periodic timer continuous-scan mode
Continuous-Scan Modes
Queue 2 cannot be programmed for externally gated continuous-scan mode.
7
to 2
17
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
QCLK cycles in binary multiples. When the interval timer single-scan mode is
NOTE
Queued Analog-to-Digital Converter (QADC)
Section 28.8.9, “Periodic/Interval
28-49
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