MCF5216CVF66J Freescale Semiconductor, MCF5216CVF66J Datasheet - Page 411
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MCF5216CVF66J
Manufacturer Part Number
MCF5216CVF66J
Description
IC MCU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF521xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5216CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
142
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF521x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
M52210DEMO, M52211EVB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5216CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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22.3.5
The QAR is used to specify the location in the QSPI RAM that read and write operations affect. As shown
in
is located at 0x10 to 0x1F, and the command RAM is located at 0x20 to 0x2F. (These addresses refer to
the QSPI RAM space, not the device memory map.)
Freescale Semiconductor
WCEFB
WCEFE
ABRTB
ABRTE
ABRTL
SPIFE
WCEF
ABRT
Field
SPIF
Section 22.4.1, “QSPI
7–4
15
14
13
12
11
10
9
8
3
2
1
0
Write collision access error enable. A write collision occurs during a data transfer when the RAM entry containing
the current command is written to by the CPU with the QDR. When this bit is asserted, the write access to QDR
results in an access error.
Abort access error enable. An abort occurs when QDLYR[SPE] is cleared during a transfer. When set, an attempt to
clear QDLYR[SPE] during a transfer results in an access error.
Reserved, must be cleared.
Abort lock-out. When set, QDLYR[SPE] cannot be cleared by writing to the QDLYR. QDLYR[SPE] is only cleared by
the QSPI when a transfer completes.
Write collision (WCEF) interrupt enable.
0 Write collision interrupt disabled
1 Write collision interrupt enabled
Abort (ABRT) interrupt enable.
0 Abort interrupt disabled
1 Abort interrupt enabled
Reserved, must be cleared.
QSPI finished (SPIF) interrupt enable.
0 SPIF interrupt disabled
1 SPIF interrupt enabled
Reserved, must be cleared.
Write collision error flag. Indicates that an attempt has been made to write to the RAM entry that is currently being
executed. Writing a 1 to this bit (w1c) clears it and writing 0 has no effect.
Abort flag. Indicates that QDLYR[SPE] has been cleared by the user writing to the QDLYR rather than by completion
of the command queue by the QSPI. Writing a 1 to this bit (w1c) clears it and writing 0 has no effect.
Reserved, must be cleared.
QSPI finished flag. Asserted when the QSPI has completed all the commands in the queue. Set on completion of
the command pointed to by QWR[ENDQP], and on completion of the current command after assertion of
QWR[HALT]. In wraparound mode, this bit is set every time the command pointed to by QWR[ENDQP] is completed.
Writing a 1 to this bit (w1c) clears it and writing 0 has no effect.
QSPI Address Register (QAR)
A read or write to the QSPI RAM causes QAR to increment. However, the
QAR does not wrap after the last queue entry within each section of the
RAM. The application software must manage address range errors.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
RAM”, the transmit RAM is located at addresses 0x0 to 0xF, the receive RAM
Table 22-6. QIR Field Descriptions
NOTE
Description
Queued Serial Peripheral Interface (QSPI)
22-7
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