MCF5216CVF66J Freescale Semiconductor, MCF5216CVF66J Datasheet - Page 259
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MCF5216CVF66J
Manufacturer Part Number
MCF5216CVF66J
Description
IC MCU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF521xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5216CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
142
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF521x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
M52210DEMO, M52211EVB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5216CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Signal Descriptions
14.2.1.1 Address Bus (A[23:0])
The 24 dedicated address signals, A[23:0], define the address of external byte, word, longword and
16-byte burst accesses. These three-state outputs are the 24 lsbs of the internal 32-bit address bus. The
address lines also serve as the SDRAM addressing, providing multiplexed row and column address
signals.
These pins are configured for GPIO ports F, G and H in single-chip mode. The A[23:21] pins can also be
configured for CS[6:4].
14.2.1.2 Data Bus (D[31:0])
These three-state bidirectional signals provide the general purpose data path between the MCU and all
other devices. Data is sampled by the processor on the rising CLKOUT edge. The data bus port width and
wait states are initially defined for the external boot chip select, CS0, by D[19:18] during chip
configuration at reset. The port width for each chip select and SDRAM bank is programmable. The data
bus uses a default configuration if none of the chip selects or SDRAM bank match the address decode. The
default configuration is a 32-bit port with external termination and burst-inhibited transfers. The data bus
can transfer byte, word, or longword data widths. All 32 data bus signals are driven during writes,
regardless of port width and operand size.
D[26:24, 21, 19:16] are used during chip configuration as inputs to configure the functions as described in
Chapter 27, “Chip Configuration Module
(CCM).”
These pins are configured as GPIO ports A, B, C and D in single-chip mode.
14.2.1.3 Byte Strobes (BS[3:0])
The byte strobes (BS[3:0]) define the byte lane of data on the data bus. During accesses, these outputs act
as the byte select signals that indicate valid data is to be latched or driven onto a byte lane when driven
low. For SRAM or Flash devices, the BS[3:0] outputs should be connected to individual byte strobe
signals. For SDRAM devices, the BS[3:0] should be connected to individual SDRAM DQM signals. Note
that most SDRAMs associate DQM3 with the MSB, in which case BS3 is connected to the SDRAM's
DQM3 input.
These pins can also be configured as GPIO PJ[7:4].
14.2.1.4 Output Enable (OE)
This output signal indicates when an external device can drive data during external read cycles.
This pin can also be configured as GPIO PE7.
14.2.1.5 Transfer Acknowledge (TA)
This signal indicates that the external data transfer is complete. During a read cycle, when the processor
recognizes TA, it latches the data and then terminates the bus cycle. During a write cycle, when the
processor recognizes TA, the bus cycle is terminated. If all bus cycles support fast termination, TA can be
tied low.
This pin can also be configured as GPIO PE6.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Freescale Semiconductor
14-19
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