MCF5216CVF66J Freescale Semiconductor, MCF5216CVF66J Datasheet - Page 379
MCF5216CVF66J
Manufacturer Part Number
MCF5216CVF66J
Description
IC MCU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF521xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5216CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
142
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF521x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
M52210DEMO, M52211EVB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5216CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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20.5.11 GPT System Control Register 2 (GPTSCR2)
Freescale Semiconductor
Bit(s)
Bit(s)
7–4
3–0
7
6
5
4
3
Address
Reset
Field
R/W
Name
Name
RDPT
TCRE
PUPT
CnI
TOI
—
—
Figure 20-13. GPT System Control Register 2 (GPTSCR2)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
TOI
7
Reserved, should be cleared.
Channel interrupt enable. Enables the C[3:0]F flags in GPT flag register 1 to generate
interrupt requests for each channel. These bits are read anytime, write anytime.
1 Corresponding channel interrupt requests enabled
0 Corresponding channel interrupt requests disabled
Enables timer overflow interrupt requests.
1 Overflow interrupt requests enabled
0 Overflow interrupt requests disabled
Reserved, should be cleared.
Enables pull-up resistors on the GPT ports when the ports are configured as inputs.
1 Pull-up resistors enabled
0 Pull-up resistors disabled
GPT drive reduction. Reduces the output driver size.
1 Output drive reduction enabled
0 Output drive reduction disabled
Enables a counter reset after a channel 3 compare.
1 Counter reset enabled
0 Counter reset disabled
Note: When the GPT channel 3 registers contain 0x0000 and TCRE is set, the GPT
counter registers remain at 0x0000 all the time. When the GPT channel 3 registers
contain 0xFFFF and TCRE is set, TOF does not get set even though the GPT counter
registers go from 0xFFFF to 0x0000.
Table 20-14. GPTSCR2 Field Descriptions
Table 20-13. GPTIE Field Descriptions
—
6
IPSBAR + 0x1A_000D, 0x1B_000D
PUPT
5
RDPT
0000_0000
4
R/W
TCRE
Description
3
Description
General Purpose Timer Modules (GPTA and GPTB)
2
PR
0
20-11
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