C8051F121-GQR Silicon Laboratories Inc, C8051F121-GQR Datasheet - Page 134
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C8051F121-GQR
Manufacturer Part Number
C8051F121-GQR
Description
IC 8051 MCU FLASH 128K 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F12xr
Specifications of C8051F121-GQR
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
C8051F1x
Core
8051
Data Bus Width
8 bit
Data Ram Size
8.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
32
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F120DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
12 bit, 2 Channel
For Use With
336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F121-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
134
Bits 7
Bits 5
Bits 3
Bits 1
*Note: On the C8051F132/3, the COBANK and IFBANK bits should both remain set to the default setting of ‘01’ to
Figure 11.3. Address Memory Map for Instruction Fetches (128 kB Flash Only)
R/W
Bit7
-
–
–
–
–
6: Reserved.
4: COBANK: Constant Operations Bank Select.
2: Reserved.
0: IFBANK: Instruction Fetch Operations Bank Select.
ensure proper device functionality.
These bits select which Flash bank is targeted during constant operations (MOVC and Flash
MOVX) involving addresses 0x8000 to 0xFFFF. These bits are ignored when accessing the
Scratchpad memory areas (see
00: Constant Operations Target Bank 0 (note that Bank 0 is also mapped between 0x0000 to
0x7FFF).
01: Constant Operations Target Bank 1.
10: Constant Operations Target Bank 2.
11: Constant Operations Target Bank 3.
These bits select which Flash bank is used for instruction fetches involving addresses 0x8000 to
0xFFFF. These bits can only be changed from code in Bank 0 (see Figure 11.3).
00: Instructions Fetch From Bank 0 (note that Bank 0 is also mapped between 0x0000 to
0x7FFF).
01: Instructions Fetch From Bank 1.
10: Instructions Fetch From Bank 2.
11: Instructions Fetch From Bank 3.
SFR Definition 11.1. PSBANK: Program Space Bank Select
R/W
Bit6
-
Address
0xFFFF
0x7FFF
Internal
0x8000
0x0000
R/W
Bit5
COBANK
IFBANK = 0
Bank 0
Bank 0
R/W
Bit4
Section “15. Flash Memory” on page 199
IFBANK = 1
Bank 1
Bank 0
Rev. 1.4
R/W
Bit3
-
IFBANK = 2
Bank 2
Bank 0
R/W
Bit2
-
IFBANK = 3
Bank 3
Bank 0
R/W
Bit1
IFBANK
SFR Address:
SFR Page:
R/W
Bit0
).
0xB1
All Pages
00010001
Reset Value
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