C8051F121-GQR Silicon Laboratories Inc, C8051F121-GQR Datasheet - Page 76
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C8051F121-GQR
Manufacturer Part Number
C8051F121-GQR
Description
IC 8051 MCU FLASH 128K 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F12xr
Specifications of C8051F121-GQR
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
C8051F1x
Core
8051
Data Bus Width
8 bit
Data Ram Size
8.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
32
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F120DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
12 bit, 2 Channel
For Use With
336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F121-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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C8051F130/1/2/3
6.2.2. Tracking Modes
The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0
input is continuously tracked when a conversion is not in progress. When the AD0TM bit is logic 1, ADC0
operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking
period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR0 signal is used to initiate
conversions in low-power tracking mode, ADC0 tracks only when CNVSTR0 is low; conversion begins on
the rising edge of CNVSTR0 (see Figure 6.3). Tracking can also be disabled (shutdown) when the entire
chip is in low power standby or sleep modes. Low-power track-and-hold mode is also useful when AMUX
or PGA settings are frequently changed, to ensure that settling time requirements are met (see
“6.2.3. Settling Time Requirements” on page 77
76
Timer 2, Timer 3 Overflow;
(AD0CM[1:0]=00, 01, 11)
Write '1' to AD0BUSY
(AD0CM[1:0]=10)
SAR Clocks
SAR Clocks
SAR Clocks
ADC0TM=1
ADC0TM=0
ADC0TM=1
ADC0TM=0
CNVSTR0
Figure 6.3. ADC0 Track and Conversion Example Timing
A. ADC Timing for External Trigger Source
B. ADC Timing for Internal Trigger Sources
Low Power
Low Power
or Convert
or Convert
Track or
Convert
Track Or Convert
1
1
Track
2
2
Track
3
3
4
4
1
5
5
2
6
6
3
7
7
Rev. 1.4
Convert
).
4
8
8
5
9
9
10 11 12 13 14 15 16 17 18 19
10 11 12 13 14 15 16
6
Convert
7
Convert
Convert
8
9
10 11 12 13 14 15 16
Low Power Mode
Track
Low Power Mode
Track
Section
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