C8051F121-GQR Silicon Laboratories Inc, C8051F121-GQR Datasheet - Page 170
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C8051F121-GQR
Manufacturer Part Number
C8051F121-GQR
Description
IC 8051 MCU FLASH 128K 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F12xr
Specifications of C8051F121-GQR
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
C8051F1x
Core
8051
Data Bus Width
8 bit
Data Ram Size
8.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
32
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F120DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
12 bit, 2 Channel
For Use With
336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F121-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
170
Bits 7 – 6: UNUSED: Read = 00b, Write = don’t care.
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
Note:
Bit7
R
-
MAC0SC: Accumulator Shift Control.
When set to 1, the 40-bit MAC0 Accumulator register will be shifted during the next SYSCLK
cycle. The direction of the shift (left or right) is controlled by the MAC0RS bit.
This bit is cleared to ‘0’ by hardware when the shift is complete.
MAC0SD: Accumulator Shift Direction.
This bit controls the direction of the accumulator shift activated by the MAC0SC bit.
0: MAC0 Accumulator will be shifted left.
1: MAC0 Accumulator will be shifted right.
MAC0CA: Clear Accumulator.
This bit is used to reset MAC0 before the next operation.
When set to ‘1’, the MAC0 Accumulator will be cleared to zero and the MAC0 Status regis-
ter will be reset during the next SYSCLK cycle.
This bit will be cleared to ‘0’ by hardware when the reset is complete.
MAC0SAT: Saturate Rounding Register.
This bit controls whether the Rounding Register will saturate. If this bit is set and a Soft
Overflow occurs, the Rounding Register will saturate. This bit does not affect the operation
of the MAC0 Accumulator. See Section 12.6 for more details about rounding and saturation.
0: Rounding Register will not saturate.
1: Rounding Register will saturate.
MAC0FM: Fractional Mode.
This bit selects between Integer Mode and Fractional Mode for MAC0 operations.
0: MAC0 operates in Integer Mode.
1: MAC0 operates in Fractional Mode.
MAC0MS: Mode Select
This bit selects between MAC Mode and Multiply Only Mode.
0: MAC (Multiply and Accumulate) Mode.
1: Multiply Only Mode.
The contents of this register should not be changed by software during the first two MAC0
pipeline stages.
Bit6
R
-
SFR Definition 12.1. MAC0CF: MAC0 Configuration
MAC0SC MAC0SD MAC0CA MAC0SAT MAC0FM MAC0MS 00000000
R/W
Bit5
R/W
Bit4
Rev. 1.4
R/W
Bit3
R/W
Bit2
R/W
Bit1
SFR Address: 0xC3
SFR Page: 3
R/W
Bit0
Reset Value
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