C8051F121-GQR Silicon Laboratories Inc, C8051F121-GQR Datasheet - Page 235
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C8051F121-GQR
Manufacturer Part Number
C8051F121-GQR
Description
IC 8051 MCU FLASH 128K 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F12xr
Specifications of C8051F121-GQR
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
C8051F1x
Core
8051
Data Bus Width
8 bit
Data Ram Size
8.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
32
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F120DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
12 bit, 2 Channel
For Use With
336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F121-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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18. Port Input/Output
The devices are fully integrated mixed-signal System on a Chip MCUs with 64 digital I/O pins (100-pin
TQFP packaging) or 32 digital I/O pins (64-pin TQFP packaging), organized as 8-bit Ports. All ports are
both bit- and byte-addressable through their corresponding Port Data registers. All Port pins are 5 V-toler-
ant, and all support configurable Open-Drain or Push-Pull output modes and weak pullups. A block dia-
gram of the Port I/O cell is shown in Figure 18.1. Complete Electrical Specifications for the Port I/O pins
are given in Table 18.1.
/WEAK-PULLUP
PUSH-PULL
/PORT-OUTENABLE
PORT-OUTPUT
ANALOG INPUT
PORT-INPUT
Analog Select
(Ports 1, 2, and 3)
Figure 18.1. Port I/O Cell Block Diagram
Rev. 1.4
C8051F120/1/2/3/4/5/6/7
DGND
VDD
C8051F130/1/2/3
VDD
(WEAK)
PORT
PAD
235
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