C8051F121-GQR Silicon Laboratories Inc, C8051F121-GQR Datasheet - Page 282
C8051F121-GQR
Manufacturer Part Number
C8051F121-GQR
Description
IC 8051 MCU FLASH 128K 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F12xr
Specifications of C8051F121-GQR
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
C8051F1x
Core
8051
Data Bus Width
8 bit
Data Ram Size
8.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
32
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F120DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
12 bit, 2 Channel
For Use With
336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F121-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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282
Bits 7–0: SPI0DAT: SPI0 Transmit and Receive Data.
Bits 7–0: SCR7–SCR0: SPI0 Clock Rate.
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
f
SCK
SCR7
f
R/W
Bit7
SCK
R/W
Bit7
=
=
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to SPI0DAT
places the data into the transmit buffer and initiates a transfer when in Master Mode. A read
of SPI0DAT returns the contents of the receive buffer.
These bits determine the frequency of the SCK output when the SPI0 module is configured
for master mode operation. The SCK clock frequency is a divided version of the system
clock, and is given in the following equation, where SYSCLK is the system clock frequency
and SPI0CKR is the 8-bit value held in the SPI0CKR register.
for 0 <= SPI0CKR <= 255
200kHz
------------------------- -
2
2000000
SCR6
R/W
Bit6
R/W
Bit6
4
+
SFR Definition 20.3. SPI0CKR: SPI0 Clock Rate
1
SFR Definition 20.4. SPI0DAT: SPI0 Data
SCR5
R/W
Bit5
R/W
Bit5
f
SCK
SCR4
R/W
Bit4
R/W
Bit4
=
---------------------------------------------- -
2
Rev. 1.4
SCR3
R/W
Bit3
R/W
Bit3
SPI0CKR
SYSCLK
SCR2
R/W
Bit2
R/W
Bit2
+
1
SCR1
R/W
Bit1
R/W
Bit1
SFR Address:
SFR Address:
SFR Page:
SFR Page:
SCR0
R/W
Bit0
R/W
Bit0
0x9B
0
00000000
0x9D
0
Reset Value
00000000
Reset Value
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