DF2160BVTE10 Renesas Electronics America, DF2160BVTE10 Datasheet - Page 423

• Manufacturer Part Number: DF2160BVTE10
• Description: IC H8S MCU FLASH 64K 144TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2160BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 114
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2160BVTE10; HD64F2160BVTE10

Note:
Bit
4
3
2
1
0
Bit Name
FER
PER
TEND
MPB
MPBT
* Only 0 can be written, to clear the flag.
Initial Value
0
0
1
0
0
R/W
R/(W) *
R/(W) *
R
R
R/W
Section 15 Serial Communication Interface (SCI and IrDA)
Description
Framing Error
[Setting condition]
When the stop bit is 0
[Clearing condition]
When 0 is written to FER after reading FER = 1
In 2-stop-bit mode, only the first stop bit is checked.
Parity Error
[Setting condition]
When a parity error is detected during reception
[Clearing condition]
When 0 is written to PER after reading PER = 1
Transmit End
[Setting conditions]
[Clearing conditions]
Multiprocessor Bit
MPB stores the multiprocessor bit in the receive
frame. When the RE bit in SCR is cleared to 0 its
previous state is retained.
Multiprocessor Bit Transfer
MPBT stores the multiprocessor bit to be added to
the transmit frame.
When the TE bit in SCR is 0
When TDRE = 1 at transmission of the last bit of
a 1-byte serial transmit character
When 0 is written to TDRE after reading
TDRE = 1
When a TXI interrupt request is issued allowing
the DTC to write data to TDR
Rev. 3.00 Mar 21, 2006 page 367 of 788
REJ09B0300-0300