DF2160BVTE10 Renesas Electronics America, DF2160BVTE10 Datasheet - Page 518

• Manufacturer Part Number: DF2160BVTE10
• Description: IC H8S MCU FLASH 64K 144TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2160BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 114
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2160BVTE10; HD64F2160BVTE10

Section 16 I
Rev. 3.00 Mar 21, 2006 page 462 of 788
REJ09B0300-0300
Figure 16.21 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0)
2
C Bus Interface (IIC) (Optional)
Read AASX, AAS and ADZ in ICSR
No
No
and TRS = 0 in ICCR
Set HNDS = 0 in ICXR
Set ACKB = 0 in ICSR
Set ACKB = 1 in ICSR
Slave receive mode
Read IRIC in ICCR
Clear IRIC in ICCR
Clear IRIC in ICCR
Clear IRIC in ICCR
Read IRIC in ICCR
Clear IRIC in ICCR
Read TRS in ICCR
Wait for one frame
and ADZ = 1?
Set MST = 0
(n-2)th-byte
ICDRF = 1?
ESTP = 1 or
ICDRF = 1?
ICDRF = 1?
Read ICDR
Read ICDR
STOP = 1?
Read ICDR
reception?
IRIC = 1?
IRIC = 1?
TRS = 1?
AAS = 1
End
Yes
No
Yes
Yes
No
No
Yes
No
Yes
Yes
No
No
No
Yes
* n: Address + total number of bytes received
Slave transmit mode
[3] to [7] Wait for one byte to be received (slave address + R/W)
[11] Wait for one byte to be received
[1] Select slave receive mode.
General call address processing
[10] Read the receive data. The first read is a dummy read.
[9] Wait for ACKB setting and set acknowledge data
[12] Detect stop condition
[2] Read the receive data remaining unread.
[8] Clear IRIC
[13] Clear IRIC
[14] Read the last receive data
[15] Clear IRIC
(after the rise of the 9th clock of (n-1)th byte data)
for the last reception
(Set IRIC at the rise of the 9th clock)
(Set IRIC at the rise of the 9th clock)
* Description omitted