DF2160BVTE10 Renesas Electronics America, DF2160BVTE10 Datasheet - Page 633

• Manufacturer Part Number: DF2160BVTE10
• Description: IC H8S MCU FLASH 64K 144TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2160BVTE10

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: Host Interface (LPC), I²C, IrDA, SCI, X-Bus
• Peripherals: PWM, WDT
• Number Of I /o: 114
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2160BVTE10; HD64F2160BVTE10

19.6
19.6.1
LPC operation can be enabled or disabled using the module stop control register. The initial
setting is for LPC operation to be halted. Register access is enabled by canceling module stop
mode. For details, refer to section 26, Power-Down Modes.
19.6.2
The host interface provides buffering of asynchronous data from the host processor and slave
processor (this LSI), but an interface protocol that uses the flags in STR must be followed to avoid
data contention. For example, if the host and slave processor both try to access IDR or ODR at the
same time, the data will be corrupted. To prevent simultaneous accesses, IBF and OBF must be
used to allow access only to data for which writing has finished.
No
No
Usage Notes
Module Stop Mode Setting
Notes on Using Host Interface
Write 1 to IRQ1E1
ODR1 write
transferred?
OBF1 = 0?
All bytes
Figure 19.8 HIRQ Flowchart (Example of Channel 1)
Yes
Yes
Slave CPU
SERIRQ IRQ1 output
source clearance
SERIRQ IRQ1
Section 19 Host Interface LPC Interface (LPC)
Rev. 3.00 Mar 21, 2006 page 577 of 788
Hardware operation
Software operation
Interrupt initiation
Master CPU
ODR1 read
REJ09B0300-0300