HD6417034AFI20V Renesas Electronics America, HD6417034AFI20V Datasheet - Page 230

MCU 5V 0K I-TEMP PB-FREE 112-QFP

HD6417034AFI20V

Manufacturer Part Number
HD6417034AFI20V
Description
MCU 5V 0K I-TEMP PB-FREE 112-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet

Specifications of HD6417034AFI20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417034AFI20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 9 Direct Memory Access Controller (DMAC)
Rev. 7.00 Jan 31, 2006 page 202 of 658
REJ09B0272-0700
Two types of transfers are possible in single address mode: 1) transfers between external
devices with DACK and memory-mapped external devices, and 2) transfers between external
devices with DACK and external memory. The only transfer request for either of these is the
external request (DREQ). Figure 9.7 shows the DMA transfer timing for single address mode.
The DACK output when a transfer occurs from an external device with DACK to a memory-
mapped external device is the write waveform. The DACK output when a transfer occurs from
a memory-mapped external device to an external device with DACK is the read waveform.
The settings of the acknowledge mode (AM) bits in the channel control registers (CHCR0,
CHCR1) have no effect.
Note: The read/write direction is decided by the RS3-RS0 bits in the CHCRn registers. If
RS3-RS0 = 0010, the direction is as shown in case 1 (circled number above); if RS3-
RS0 = 0011, the direction is as shown in case 2. In the Electrical Characteristics
section, DACK output (read) indicates case 1, and DACK output (write) indicates
case 2.
SuperH microcomputer
External address bus
DMAC
Figure 9.6 Data Flow in Single Address Mode
: Data flow
DREQ
DACK
External data bus
Read Write
1
2
External device
with DACK
External
memory

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