HD6417034AFI20V Renesas Electronics America, HD6417034AFI20V Datasheet - Page 385

• Manufacturer Part Number: HD6417034AFI20V
• Description: MCU 5V 0K I-TEMP PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

storage. RSR is then ready to receive the next data. This double buffering allows the SCI to
receive data continuously.
The CPU can read but not write to RDR. RDR is initialized to H'00 by a reset and in standby
mode.
13.2.3
The transmit shift register (TSR) transmits serial data. The SCI loads transmit data from the
transmit data register (TDR) into TSR, then transmits the data serially from the TxD pin, LSB (bit
0) first. After transmitting one data byte, the SCI automatically loads the next transmit data from
TDR into TSR and starts transmitting again. If the TDRE bit in SSR is 1, however, the SCI does
not load the TDR contents into TSR. The CPU cannot read or write to TSR directly.
13.2.4
The transmit data register (TDR) is an eight-bit register that stores data for serial transmission.
When the SCI detects that the transmit shift register (TSR) is empty, it moves transmit data written
in TDR into TSR and starts serial transmission. Continuous serial transmission is possible by
writing the next transmit data in TDR during serial transmission from TSR.
The CPU can always read and write to TDR. TDR is initialized to H'FF by a reset and in standby
mode.
Bit
Initial value
Read/Write
Bit
Read/Write
Bit
Initial value
Read/Write
Transmit Shift Register
Transmit Data Register
R/W
—
R
7
0
7
7
1
R/W
—
R
6
0
6
6
1
R/W
—
R
5
0
5
5
1
Section 13 Serial Communication Interface (SCI)
R/W
—
R
4
0
4
4
1
Rev. 7.00 Jan 31, 2006 page 357 of 658
R/W
—
R
3
0
3
3
1
R/W
—
R
2
0
2
2
1
REJ09B0272-0700
R/W
—
R
1
0
1
1
1
R/W
—
R
0
0
0
0
1