HD6417034AFI20V Renesas Electronics America, HD6417034AFI20V Datasheet - Page 406

• Manufacturer Part Number: HD6417034AFI20V
• Description: MCU 5V 0K I-TEMP PB-FREE 112-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 13 Serial Communication Interface (SCI)
Table 13.9 SMR and SCR Settings and SCI Clock Source Selection
Mode
Asynchronous
mode
Synchronous
mode
Note: * Select the function in combination with the pin function controller (PFC).
13.3.2
In asynchronous mode, each transmitted or received character begins with a start bit and ends with
a stop bit. Serial communication is synchronized one character at a time.
The transmitting and receiving sections of the SCI are independent, so full duplex communication
is possible. The transmitter and receiver are both double buffered, so data can be written and read
while transmitting and receiving are in progress, enabling continuous transmitting and receiving.
Figure 13.2 shows the general format of asynchronous serial communication. In asynchronous
serial communication, the communication line is normally held in the mark (high) state. The SCI
monitors the line and starts serial communication when the line goes to the space (low) state,
indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit
(high or low), and stop bit (high), in that order.
When receiving in asynchronous mode, the SCI synchronizes on the falling edge of the start bit.
The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate.
Receive data is latched at the center of each bit.
Rev. 7.00 Jan 31, 2006 page 378 of 658
REJ09B0272-0700
Operation in Asynchronous Mode
Bit 7:
C/A A A A
0
1
SMR
Bit 1:
CKE1
0
1
0
1
SCR Settings
Bit 0:
CKE0
0
1
0
1
0
1
0
1
Internal
External
Internal
External
Clock Source
SCI Transmit/Receive Clock
SCK Pin Function*
SCI does not use the SCK pin
Outputs a clock with frequency
matching the bit rate
Inputs a clock with frequency 16
times the bit rate
Outputs the serial clock
Inputs the serial clock