DF2377RVFQ33W Renesas Electronics America, DF2377RVFQ33W Datasheet - Page 489

• Manufacturer Part Number: DF2377RVFQ33W
• Description: IC H8S MCU FLASH 3V 384K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2377RVFQ33W

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

setting the EDA bit to 1 in EDMDR to perform transfer continuation processing. An example of
the procedure for clearing the transfer end interrupt and restarting transfer is shown in figure 8.46.
Figure 8.46 Example of Procedure for Restarting Transfer on Channel in which Transfer
[1] Write set values to the registers (transfer counter, address registers, etc.).
[2] Write 1 to the EDA bit in EDMDR to restart EXDMA operation. When 1 is written to the EDA
[3] The interrupt handling routine is ended with an RTE instruction, etc.
[4] Clear the IRF bit to 0 in EDMDR by first reading 1 from it, then writing 0.
[5] After the interrupt handling routine is ended with an RTE instruction, etc., interrupt masking is
[6] Write set values to the registers (transfer counter, address registers, etc.).
[7] Write 1 to the EDA bit in EDMDR to restart EXDMA operation.
bit, the IRF bit in EDMDR is automatically cleared to 0 and the interrupt source is cleared.
cleared.
(RTE instruction execution)
exception handling routine
End of interrupt handling
Change register settings
End of transfer restart
Transfer end interrupt
Transfer continuation
Write 1 to EDA bit
processing
processing
routine
End Interrupt Occurred
[1]
[2]
[3]
Rev.7.00 Mar. 18, 2009 page 421 of 1136
of interrupt handling routine
Section 8 EXDMA Controller (EXDMAC)
Transfer restart after end
End of interrupt handling
Change register settings
End of transfer restart
Write 1 to EDA bit
Clear IRF bit to 0
processing
routine
REJ09B0109-0700
[4]
[5]
[6]
[7]