DF2377RVFQ33W Renesas Electronics America, DF2377RVFQ33W Datasheet - Page 774

IC H8S MCU FLASH 3V 384K 144LQFP

DF2377RVFQ33W

Manufacturer Part Number
DF2377RVFQ33W
Description
IC H8S MCU FLASH 3V 384K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2377RVFQ33W

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
DF2377RVFQ33W
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
DF2377RVFQ33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 15 Serial Communication Interface (SCI, IrDA)
Smart Card Interface Mode (When SMIF in SCMR is 1)
Bit
7
6
Rev.7.00 Mar. 18, 2009 page 706 of 1136
REJ09B0109-0700
Bit Name
TDRE
RDRF
Initial Value
1
0
R/W
R/(W)*
R/(W)*
1
1
Description
Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
[Clearing conditions]
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
[Clearing conditions]
The RDRF flag is not affected and retains its
previous value when the RE bit in SCR is cleared
to 0. Exercise care because if reception of the next
data is completed while the RDRF flag is set to 1,
an overrun error occurs and receive data will be
lost.
When the TE bit in SCR is 0
When data is transferred from TDR to TSR, and
data writing to TDR is enabled.
When 0 is written to TDRE after reading TDRE
= 1
When the DMAC or DTC is activated by a TXI
interrupt request and transfers data to TDR
When serial reception ends normally and
receive data is transferred from RSR to RDR
When 0 is written to RDRF after reading RDRF
= 1
When the DMAC or DTC is activated by an RXI
interrupt and transferred data from RDR

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