UPD78F9222CS-CAC-A Renesas Electronics America, UPD78F9222CS-CAC-A Datasheet - Page 193

• Manufacturer Part Number: UPD78F9222CS-CAC-A
• Description: MCU 8BIT 4KB FLASH 20PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9222CS-CAC-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Asynchronous serial interface reception error status register 6 (ASIS6)
Address: FF93H After reset: 00H R
Cautions 2. At startup, reception enable status is entered by setting RXE6 to 1 after having set POWER6
Cautions 1. The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits of
Symbol
ASIS6
This register indicates an error status on completion of reception by serial interface UART6. It includes three
error flag bits (PE6, FE6, OVE6).
This register is read-only by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H if bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 0. 00H is read
when this register is read.
Figure 11-6. Format of Asynchronous Serial Interface Reception Error Status Register 6 (ASIS6)
3. Set POWER6 = 1
4. Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits.
5. Fix the PS61 and PS60 bits to 0 when the interface is used for LIN communication operation.
6. Make sure that TXE6 = 0 when rewriting the SL6 bit. Reception is always performed with “the
7. Make sure that RXE6 = 0 when rewriting the ISRM6 bit.
2. The first bit of the receive data is checked as the stop bit, regardless of the number of stop
3. If an overrun error occurs, the next receive data is not written to receive buffer register 6
4. Be sure to read ASIS6 before reading receive buffer register 6 (RXB6).
OVE6
to 1 and one clock of the base clock (f
operation, set POWER6 to 0 after having set RXE6 to 0.
POWER6 = 1
will not be received.
number of stop bits = 1”, and therefore, is not affected by the set value of the SL6 bit.
asynchronous serial interface operation mode register 6 (ASIM6).
bits.
(RXB6) but discarded.
PE6
FE6
7
0
0
1
0
1
0
1
If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read
If the parity of transmit data does not match the parity bit on completion of reception
If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read
If the stop bit is not detected on completion of reception
If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read
If receive data is set to the RXB register and the next reception operation is completed before the
data is read.
6
0
RXE6 = 1 is set during low-level input, reception is started and correct data
CHAPTER 11 SERIAL INTERFACE UART6
RXE6 = 1 in a state where a high level has been input to the RxD6 pin. If
5
0
User’s Manual U16898EJ6V0UD
Status flag indicating framing error
Status flag indicating overrun error
Status flag indicating parity error
4
0
XCLK6
) has elapsed.
3
0
PE6
2
When stopping reception
FE6
1
OVE6
0
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