UPD78F9222CS-CAC-A Renesas Electronics America, UPD78F9222CS-CAC-A Datasheet - Page 92

• Manufacturer Part Number: UPD78F9222CS-CAC-A
• Description: MCU 8BIT 4KB FLASH 20PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9222CS-CAC-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

90
(1) TI000 pin valid edge selected as capture trigger (CRC001 = 1, CRC000 = 1)
(2) TI010 pin valid edge selected as capture trigger (CRC001 = 0, CRC000 = 1)
Remarks 1. Setting ES010, ES000 = 1, 0 and ES110, ES100 = 1, 0 is prohibited.
Cautions 1. Set CR000 to other than 0000H in the clear & start mode entered on match between TM00
Falling edge
Rising edge
No capture operation
Falling edge
Rising edge
Both rising and falling edges
CR000 Capture Trigger
CR000 Capture Trigger
2. ES010, ES000:
2. If the new value of CR000 is less than the value of 16-bit timer counter 0 (TM00), TM00
3. The value of CR000 after 16-bit timer/event counter 00 has stopped is not guaranteed.
4. The capture operation may not be performed for CR000 set in compare mode even if a
5. When using P31 as the input pin (TI010) of the valid edge, it cannot be used as a timer
6. If the register read period and the input of the capture trigger conflict when CR000 is
7. Changing the CR000 setting during TM00 operation may cause a malfunction. To change
Table 6-2. CR000 Capture Trigger and Valid Edges of TI000 and TI010 Pins
ES110, ES100:
CRC001, CRC000: Bits 1 and 0 of capture/compare control register 00 (CRC00)
and CR000.
register is used as an external event counter. However, in the free-running mode and in
the clear & start mode using the valid edge of TI000 pin, if CR000 is set to 0000H, an
interrupt request (INTTM000) is generated when CR000 changes from 0000H to 0001H
following overflow (FFFFH).
continues counting, overflows, and then starts counting from 0 again. If the new value of
CR000 is less than the old value, therefore, the timer must be reset to be restarted after
the value of CR000 is changed.
capture trigger is input.
output pin (TO00). When using P31 as the timer output pin (TO00), it cannot be used as
the input pin (TI010) of the valid edge.
used as a capture register, the capture trigger input takes precedence and the read data
is undefined. Also, if the count stop of the timer and the input of the capture trigger
conflict, the capture trigger is undefined.
the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event Counter 00 (17) Changing
compare register during timer operation.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
This means a 1-pulse count operation cannot be performed when this
Bits 5 and 4 of prescaler mode register 00 (PRM00)
Bits 7 and 6 of prescaler mode register 00 (PRM00)
Rising edge
Falling edge
Both rising and falling edges
Falling edge
Rising edge
Both rising and falling edges
User’s Manual U16898EJ6V0UD
TI000 Pin Valid Edge
TI010 Pin Valid Edge
ES010
ES110
1
1
0
0
0
0
ES000
ES100
1
0
1
0
1
1