UPD78F9222CS-CAC-A Renesas Electronics America, UPD78F9222CS-CAC-A Datasheet - Page 213

• Manufacturer Part Number: UPD78F9222CS-CAC-A
• Description: MCU 8BIT 4KB FLASH 20PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9222CS-CAC-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
Remark T
X
(g) Noise filter of receive data
D6/P44
(h) SBF transmission
INTST6
SBTT6
T
The R
If two sampled values are the same, the output of the match detector changes, and the data is sampled as
input data.
Because the circuit is configured as shown in Figure 11-21, the internal processing of the reception operation
is delayed by two clocks from the external signal status.
When the interface is used for LIN communication operation, the SBF (Synchronous Break Field)
transmission control function is used for transmission. For the transmission operation of LIN, see Figure 11-
1 LIN Transmission Operation.
When bit 7 (POWER6) of asynchronous serial interface mode register 6 (ASIM6) is set to 1, the TxD6 pin
outputs high level. Next, when bit 6 (TXE6) of ASIM6 is set to 1, the transmission enabled status is entered,
and SBF transmission is started by setting bit 5 (SBTT6) of asynchronous serial interface control register 6
(ASICL6) to 1.
Thereafter, a low level of bits 13 to 20 (set by bits 4 to 2 (SBL62 to SBL60) of ASICL6) is output. Following
the end of SBF transmission, the transmission completion interrupt request (INTST6) is generated and
SBTT6 is automatically cleared. Thereafter, the normal transmission mode is restored.
Transmission is suspended until the data to be transmitted next is written to transmit buffer register 6 (TXB6),
or until SBTT6 is set to 1.
Base clock
X
D6
INTST6: Transmission completion interrupt request
SBTT6: Bit 5 of asynchronous serial interface control register 6 (ASICL6)
X
X
D6:
D6 signal is sampled with the base clock (f
T
X
1
D6 pin (output)
2
In
3
CHAPTER 11 SERIAL INTERFACE UART6
Figure 11-21. Noise Filter Circuit
Figure 11-22. SBF Transmission
4
Q
User’s Manual U16898EJ6V0UD
5
6
Internal signal A
Match detector
7
XCLK6
) output by the prescaler block.
8
9
10
11
In
LD_EN
12
13
Q
Stop
Internal signal B
211