UPD78F9222CS-CAC-A Renesas Electronics America, UPD78F9222CS-CAC-A Datasheet - Page 395

• Manufacturer Part Number: UPD78F9222CS-CAC-A
• Description: MCU 8BIT 4KB FLASH 20PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9222CS-CAC-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Watchdog
timer
A/D
converter
Function
When “low-
speed internal
oscillator can
be stopped by
software” is
selected by
option byte
Sampling time
and A/D
conversion time
Block diagram
ADM: A/D
converter mode
register
ADS: Analog
input channel
specification
register
ADCR: 10-bit
A/D conversion
result register
PMC2: Port
mode control
register 2
A/D converter
operations
Operating
current in
STOP mode
Details of
Function
In this mode, watchdog timer operation is stopped during HALT/STOP
instruction execution. After HALT/STOP mode is released, counting is started
again using the operation clock of the watchdog timer set before HALT/STOP
instruction execution by WDTM. At this time, the counter is not cleared to 0 but
holds its value.
The above sampling time and conversion time do not include the clock
frequency error. Select the sampling time and conversion time such that Notes
2 and 3 above are satisfied, while taking the clock frequency error into
consideration (an error margin maximum of 5% when using the high-speed
internal oscillator).
In the 78K0S/KA1+, V
converter. Be sure to connect V
The above sampling time and conversion time do not include the clock
frequency error. Select the sampling time and conversion time such that Notes
2 and 3 above are satisfied, while taking the clock frequency error into
consideration (an error margin maximum of 5% when using the high-speed
internal oscillator).
If a bit other than ADCS of ADM is manipulated while A/D conversion is stopped
(ADCS = 0) and then A/D conversion is started, execute two NOP instructions
or an instruction equivalent to two machine cycles, and set ADCS to 1.
A/D conversion must be stopped (ADCS = 0) before rewriting bits FR0 to FR2.
Be sure to clear bits 6, 2, and 1 to 0.
Be sure to clear bits 2 to 7 of ADS to 0.
When writing to the A/D converter mode register (ADM) and analog input
channel specification register (ADS), the contents of ADCR may become
undefined. Read the conversion result following conversion completion before
writing to ADM and ADS. Using timing other than the above may cause an
incorrect conversion result to be read.
When PMC20 to PMC23 are set to 1, the P20/ANI0 to P23/ANI3 pins cannot be
used as port pins. Be sure to set the pull-up resistor option registers (PU20 to
PU23) to 0 for the pins set to A/D converter mode.
Make sure the period of <1> to <4> is 1 s or more.
It is no problem if the order of <1> and <2> is reversed.
<1> can be omitted. However, ignore the data resulting from the first
conversion after <4> in this case.
The period from <5> to <8> differs from the conversion time set using bits 5 to 3
(FR2 to FR0) of ADM. The period from <7> to <8> is the conversion time set
using FR2 to FR0.
To satisfy the DC characteristics of the supply current in the STOP mode, clear
bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0
before executing the STOP instruction.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16898EJ6V0UD
SS
functions alternately as the ground potential of the A/D
SS
to a stabilized GND (= 0 V).
Cautions
p. 157
p. 163
p. 164
p. 168
p. 169
p. 169
p. 169
p. 169
p. 169
p. 170
pp. 171,
175
pp. 171,
175
p. 175
p. 175
p. 178
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