UPD70F3739GC-UEU-AX Renesas Electronics America, UPD70F3739GC-UEU-AX Datasheet - Page 706
UPD70F3739GC-UEU-AX
Manufacturer Part Number
UPD70F3739GC-UEU-AX
Description
MCU 32BIT V850ES/JX3 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3r
Datasheet
1.UPD70F3739GC-UEU-AX.pdf
(889 pages)
Specifications of UPD70F3739GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
32MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3739GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 706 of 889
- Download datasheet (11Mb)
V850ES/JG3
R01UH0015EJ0300 Rev.3.00
Sep 30, 2010
Item
Subclock oscillator
Internal oscillator
PLL
CPU
DMA
Interrupt controller
Timer P (TMP0 to TMP5)
Timer Q (TMQ0)
Timer M (TMM0)
Watch timer
Watchdog timer 2
Serial interface
A/D converter
D/A converter
Real-time output function (RTO)
Key interrupt function (KR)
CRC operation circuit
External bus interface
Port function
Internal data
Note Be sure to stop the PLL (PLLCTL.PLLON bit = 0) before stopping the main clock.
Caution When the CPU is operating on the subclock and main clock oscillation is stopped, accessing a
Setting of Subclock Operation Mode
register in which a wait occurs is disabled. If a wait is generated, it can be released only by reset
(see 3.4.8 (2)).
CSIB0 to CSIB4
I
UARTA0 to UARTA2
2
C00 to I
2
C02
Table 21-10. Operating Status in Subclock Operation Mode
Oscillation enabled
Oscillation enabled
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
See 2.2 Pin States.
Settable
Settable
When Main Clock Is Oscillating
Operating Status
CHAPTER 21 STANDBY FUNCTION
Stops operation
Operable when f
Operable when the SCKBn input clock is
Stops operation
Stops operation
the count clock
Operable when f
count clock
Operable when f
the count clock
selected as the count clock (n = 0 to 4)
Stops operation
Stops operation (but UARTA0 is
operable when the ASCKA0 input clock
is selected)
Stops operation
Stops operation (output held)
When Main Clock Is Stopped
Note
R
XT
R
/8 or f
or f
is selected as the
XT
XT
is selected as
is selected as
Page 690 of 870
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