UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 1240
UPD70F3769GF-GAT-AX
Manufacturer Part Number
UPD70F3769GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3769GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3769GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
Non-maskable interrupt request
signal
Maskable interrupt request signal
Item
Subclock oscillator (f
Internal oscillator (f
PLL
CPU
DMA controller
Interrupt controller
Timer
Real-time counter (RTC)
Watchdog timer (WDT2)
Serial interface
A/D converter
D/A converter
Real-time output function (RTO)
Key interrupt function (KR)
CRC operation circuit
External bus interface
Port function
Internal data
USB function
USB host
(2) Releasing sub-IDLE mode by reset
Notes 1. Be sure to stop the PLL (PLLCTL.PLLON bit = 0) before stopping the main clock.
The same operation as the normal reset operation is performed.
Release Source
2. To realize low power consumption, stop the A/D and D/A converters before shifting to the sub-IDLE mode.
Setting of Sub-IDLE Mode
Table 25-11. Operation After Releasing Sub-IDLE Mode by Interrupt Request Signal
R
TAA0 to TAA5
TAB0, TAB1
TMM0 to TMM3
TMT0
CSIF0 to CSIF4
I
UARTC0 to UARTC4
2
)
XT
C00 to I
)
2
C02
Execution branches to the handler address.
Execution branches to the handler address
or the next instruction is executed.
Table 25-12. Operating Status in Sub-IDLE Mode
Oscillation enabled
Oscillation enabled
Operable
Stops operation
Stops operation
Stops operation
Stops operation
Stops operation
Operable when f
Stops operation
Operable
Operable when f
Operable when the SCKFn input clock is selected as the count clock (n = 0 to 4)
Stops operation
Stops operation (but UARTC0 is operable when the ASCKC0 input clock is selected)
Holds operation (conversion result held)
Holds operation (output held
Stops operation (output held)
Operable
Stops operation
See CHAPTER 5 BUS CONTROL FUNCTION. (same operation status as IDLE
mode).
Retains status before sub-IDLE mode was set
The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before the sub-IDLE mode was set.
Stops operation
Stops operation
Interrupt Enabled (EI) Status
When Main Clock Is Oscillating
R
R
/8 or f
or f
XT
XT
is selected as the count clock
is selected as the count clock
Note 2
)
Operating Status
Note 2
The next instruction is executed.
CHAPTER 25 STANDBY FUNCTION
Stops operation
Operable when f
count clock
Interrupt Disabled (DI) Status
When Main Clock Is Stopped
Note 1
XT
is selected as the
Page 1240 of 1408
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