UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 1276

• Manufacturer Part Number: UPD70F3769GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-U 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3769GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
FLMD0
FLMD1
VDD
GND
CLK
RESET
SI/RxD
SO/TxD
SCK
HS
Signal Name
Notes 1. Wire these pins as shown in Figures 31-6 and 31-7, or connect then to GND via pull-down resistor on board.
Remark
2. Clock cannot be supplied via the CLK pin of the flash memory programmer. Create an oscillator on board
and supply the clock.
×: Does not have to be connected.
Output
Output
Output
Output
Input
Output
Output
Input
: Must be connected.
I/O
−
−
Table 31-5. Signal Connections of Flash Memory Programmer (PG-FP5)
Write enable/disable
Write enable/disable
V
Ground
Clock output to V850ES/JG3-U and
V850ES/JH3-U
Reset signal
Receive signal
Transmit signal
Transfer clock
Handshake signal for CSIF0 + HS, CSIF3
+ HS communication
DD
PG-FP5
voltage generation/voltage monitor
Pin Function
FLMD0
FLMD1
V
V
X1, X2
RESET
SOF0, SOF3/
TXDC0
SIF0, SIF3/
RXDC0
SCKF0, SCKF3
P913
V850ES/JG3-U,
V850ES/JH3-U
DD
SS
Pin Name
UARTC0
CHAPTER 31 FLASH MEMORY
×
Note 2
Note 1
×
×
Processing for Connection
CSIF0,
CSIF3
×
Note 2
×
Note 1
Page 1276 of 1408
CSIF0 + HS,
CSIF3 + HS
×
Note 2
Note 1