UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 229

• Manufacturer Part Number: UPD70F3769GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-U 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3769GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(12) Noise elimination control register (TANFC)
Digital noise elimination can be selected for the TIAAn0 and TIAAn1 pins. The noise elimination setting is selected
using the TANFC register.
When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among f
and f
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
Caution Time equal to the sampling clock × 3 clocks is required until the digital noise eliminator is
Remark
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/4. Sampling is performed 3 times.
TANFC
After reset: 00H
initialized after the sampling clock has been changed. If the valid edge of TIAAn0 and TIAAn1 is
input after the sampling clock has been changed and before the time of the sampling clock × 3
clocks passes, therefore, an interrupt request signal may be generated. Therefore, when using
the external trigger function, the external event function, and the capture trigger function of TAA,
enable TAA operation after the time of the sampling clock × 3 clocks has elapsed.
n = 0 to 3, 5
Remarks 1. Since sampling is performed 3 times, the noise width for reliably eliminating
TANFEN
TANFEN
TANFC0
0
1
0
1
Does not perform digital noise elimination
Performs digital noise elimination
f
f
2. In the case of noise with a width smaller than 2 sampling clocks, an
R/W
XX
XX
/4
0
noise is 2 sampling clocks.
interrupt request signal is generated if noise synchronized with the
sampling clock is input.
Address: FFFFF724H
0
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Setting of digital noise elimination
0
Digital sampling clock
0
0
0
TANFC0
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