UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 321

• Manufacturer Part Number: UPD70F3769GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-U 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3769GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-U, V850ES/JH3-U
7.8
capture registers (TAA0CCSn = 1).
timer) to use them as a 32-bit capture timer by cascade connection.
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
This section explains an operation of connecting two channels of TAA in cascade to form a 32-bit capture timer.
For cascade connection, the free-running timer mode must be set and all the capture/compare registers must be set as
Combinations of TAA channels that can be connected in cascade are shown in the following table.
In the following example, TAA1 is used as the lower timer (master timer) and TAA0 is used as the higher timer (slave
[Lower timer TAA1]
Capture signal 1
Capture signal 0
Cascade Connection
(TIAA11)
(TIAA10)
selection
Operation enable
Count
clock
bit (TAA1CE)
detection
detection
Edge
Edge
Lower capture interrupt 0
(INTTAA1CC0)
Lower Timer (Master Timer)
Lower capture interrupt 1
Lower capture register 1
Lower capture register 0
Lower timer counter
Figure 7-50. Cascade Connection Example
(INTTAA1CC1)
(TAA1CCR1)
(TAA1CCR0)
Table 7-11. Cascade Connection of TAA
TAA1
TAA3
Lower overflow interrupt
(INTTAA1OV)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
detection
FFFFH
signal
Higher Timer (Slave Timer)
[Higher timer TAA0]
TAA0
TAA2
Higher capture register 0
Higher capture register 1
Higher timer counter
(TAA0CCR0)
(TAA0CCR1)
Higher overflow interrupt
(INTTAA0OV)
Page 321 of 1408