UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 189

• Manufacturer Part Number: UPD70F3769GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-U 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3769GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-U, V850ES/JH3-U
5.5.4
wait insertion is set for each chip select area (CS0, CS2, CS3).
address-hold wait is inserted, it seems that the low-clock period of the T1 state is extended by 1 clock.
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
Address-setup or address-hold waits to be inserted in each bus cycle can be set by using the AWC register. Address
If an address setup wait is inserted, it seems that the high-clock period of the T1 state is extended by 1 clock. If an
(1) Address wait control register (AWC)
The AWC register can be read or written in 16-bit units.
Reset sets this register to FFFFH.
Cautions 1. Address-setup wait and address-hold wait cycles are not inserted when the internal ROM area,
Programmable address wait function
Note
Caution Be sure to set bits 15 to 8 to “1”.
2. Write to the AWC register after reset, and then do not change the set values. Also, do not
After reset:
AWC
It is recommended to clear the AHW1 bit and the ASW1 bit to 0.
internal RAM area, and on-chip peripheral I/O areas are accessed.
access an external memory area until the initial settings of the AWC register are complete.
AHW3
AHWn
ASWn
15
FFFFH
1
0
1
0
1
7
CS3
Not inserted
Inserted
Not inserted
Inserted
ASW3
14
1
6
R/W
Specifies insertion of address-setup wait (n = 0 to 3)
Specifies insertion of address-hold wait (n = 0 to 3)
AHW2
13
Address:
1
5
CS2
ASW2
FFFFF488H
12
1
4
AHW1
11
1
3
Note
CHAPTER 5 BUS CONTROL FUNCTION
ASW1
10
1
2
Note
AHW0
9
1
1
CS0
ASW0
1
8
0
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