SAK-TC1767-256F80HL AD Infineon Technologies, SAK-TC1767-256F80HL AD Datasheet - Page 11

• Manufacturer Part Number: SAK-TC1767-256F80HL AD
• Description: IC MCU 32BIT FLASH 176-LQFP
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1767-256F80HL AD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 88
• Program Memory Size: 2MB (2M x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 4x10b, 32x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 176-LFQFP
• Data Bus Width: 32 bit
• Data Ram Size: 92 KB
• Interface Type: SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (12 bit, 16 Channel)
• Packages: PG-LQFP-176
• Max Clock Frequency: 80.0 MHz
• Sram (incl. Cache): 128.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 2.0 MB
• For Use With: B158-H8539-G2-X-7600IN - KIT STARTER TC176X SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SP000442086

2
This Data Sheet describes the Infineon TC1767, a 32-bit microcontroller DSP, based on
the Infineon TriCore Architecture.
2.1
This document is designed to be read primarily by design engineers and software
engineers who need a detailed description of the interactions of the TC1767 functional
units, registers, instructions, and exceptions.
This TC1767 Data Sheet describes the features of the TC1767 with respect to the
TriCore Architecture. Where the TC1767 directly implements TriCore architectural
functions, this manual simply refers to those functions as features of the TC1767. In all
cases where this manual describes a TC1767 feature without referring to the TriCore
Architecture, this means that the TC1767 is a direct implementation of the TriCore
Architecture.
Where the TC1767 implements a subset of TriCore architectural features, this manual
describes the TC1767 implementation, and then describes how it differs from the TriCore
Architecture. Such differences between the TC1767 and the TriCore Architecture are
documented in the section covering each such subject.
2.1.1
A complete description of the TriCore architecture is found in the document entitled
“TriCore Architecture Manual”. The architecture of the TC1767 is described separately
this way because of the configurable nature of the TriCore specification: Different
versions of the architecture may contain a different mix of systems components. The
TriCore architecture, however, remains constant across all derivative designs in order to
preserve compatibility.
This Data Sheets together with the “TriCore Architecture Manual” are required to
understand the complete TC1767 micro controller functionality.
2.1.2
This document uses the following text conventions for named components of the
TC1767:
•
•
•
Data Sheet
Functional units of the TC1767 are given in plain UPPER CASE. For example: “The
SSC supports full-duplex and half-duplex synchronous communication”.
Pins using negative logic are indicated by an overline. For example: “The external
reset pin, ESR0, has a dual function.”.
Bit
“Module_Register name.Bit field” or “Module_Register name.Bit”. For example: “The
Current CPU Priority Number bit field CPU_ICR.CCPN is cleared”. Most of the
fields
Introduction
About this Document
Related Documentations
Text Conventions
and
bits
in
registers
7
are
in
general
referenced
Introduction
V1.3, 2009-09
TC1767
as