SAK-TC1767-256F80HL AD Infineon Technologies, SAK-TC1767-256F80HL AD Datasheet - Page 14

• Manufacturer Part Number: SAK-TC1767-256F80HL AD
• Description: IC MCU 32BIT FLASH 176-LQFP
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1767-256F80HL AD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 88
• Program Memory Size: 2MB (2M x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 4x10b, 32x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 176-LFQFP
• Data Bus Width: 32 bit
• Data Ram Size: 92 KB
• Interface Type: SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (12 bit, 16 Channel)
• Packages: PG-LQFP-176
• Max Clock Frequency: 80.0 MHz
• Sram (incl. Cache): 128.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 2.0 MB
• For Use With: B158-H8539-G2-X-7600IN - KIT STARTER TC176X SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SP000442086

Table 3
Symbol
U
SV
R
32
E
PW
NC
BE
nBE
nE
2.1.5
The following acronyms and terms are used in this document:
ADC
AGPR
ALU
ASC
BCU
BROM
CAN
CMEM
CISC
CPS
CPU
Data Sheet
Abbreviations and Acronyms
Access Terms
Analog-to-Digital Converter
Address General Purpose Register
Arithmetic and Logic Unit
Asynchronous/Synchronous Serial Controller
Bus Control Unit
Boot ROM & Test ROM
Controller Area Network
PCP Code Memory
Complex Instruction Set Computing
CPU Slave Interface
Central Processing Unit
Description
Access Mode: Access permitted in User Mode 0 or 1.
Reset Value: Value or bit is not changed by a reset operation.
Access permitted in Supervisor Mode.
Read-only register.
Only 32-bit word accesses are permitted to this register/address range.
Endinit-protected register/address.
Password-protected register/address.
No change, indicated register is not changed.
Indicates that an access to this address range generates a Bus Error.
Indicates that no Bus Error is generated when accessing this address
range, even though it is either an access to an undefined address or the
access does not follow the given rules.
Indicates that no Error is generated when accessing this address or
address range, even though the access is to an undefined address or
address range. True for CPU accesses (MTCR/MFCR) to undefined
addresses in the CSFR range.
10
Introduction
V1.3, 2009-09
TC1767