SAK-TC1767-256F80HL AD Infineon Technologies, SAK-TC1767-256F80HL AD Datasheet - Page 38
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SAK-TC1767-256F80HL AD
Manufacturer Part Number
SAK-TC1767-256F80HL AD
Description
IC MCU 32BIT FLASH 176-LQFP
Manufacturer
Infineon Technologies
Series
TC17xxr
Datasheet
1.SAK-TC1767-256F80HL_AD.pdf
(126 pages)
Specifications of SAK-TC1767-256F80HL AD
Core Processor
TriCore
Core Size
32-Bit
Speed
80MHz
Connectivity
ASC, CAN, MLI, MSC, SSC
Peripherals
DMA, POR, WDT
Number Of I /o
88
Program Memory Size
2MB (2M x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.42 V ~ 1.58 V
Data Converters
A/D 4x10b, 32x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
176-LFQFP
Data Bus Width
32 bit
Data Ram Size
92 KB
Interface Type
SPI
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
88
Number Of Timers
2
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (12 bit, 16 Channel)
Packages
PG-LQFP-176
Max Clock Frequency
80.0 MHz
Sram (incl. Cache)
128.0 KByte
Can Nodes
2
A / D Input Lines (incl. Fadc)
36
Program Memory
2.0 MB
For Use With
B158-H8539-G2-X-7600IN - KIT STARTER TC176X SERIES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
SP000442086
2.4.3
The Micro Second Channel (MSC) interface provides serial communication links
typically used to connect power switches or other peripheral devices. The serial
communication link includes a fast synchronous downstream channel and a slow
asynchronous upstream channel.
of the MSC interface.
Figure 7
The downstream and upstream channels of the MSC module communicate with the
external world via nine I/O lines. Eight output lines are required for the serial
communication of the downstream channel (clock, data, and enable signals). One out of
eight input lines SDI[7:0] is used as serial data input signal for the upstream channel. The
source of the serial data to be transmitted by the downstream channel can be MSC
register contents or data that is provided on the ALTINL/ALTINH input lines. These input
lines are typically connected with other on-chip peripheral units (for example with a timer
unit such as the GPTA). An emergency stop input signal makes it possible to set bits of
the serial data stream to dedicated values in an emergency case.
Clock control, address decoding, and interrupt service request control are managed
outside the MSC module kernel. Service request outputs are able to trigger an interrupt
or a DMA request.
Data Sheet
Micro Second Channel Interface
General Block Diagram of the MSC Interface
ALTINL[15:0]
ALTINH[15:0]
EMGSTOPMSC
Decoder
Interrupt
Address
Control
Control
To DMA
Clock
SR[3:0]
f
f
MSC
CLC
16
16
4
Figure 7
(Kernel)
Module
MSC
34
shows a global view of the interface signals
8
MCB06059
FCLP
FCLN
SOP
SON
EN0
EN1
EN2
EN3
SDI[7:0]
Introduction
V1.3, 2009-09
TC1767