SAK-TC1767-256F80HL AD Infineon Technologies, SAK-TC1767-256F80HL AD Datasheet - Page 51

• Manufacturer Part Number: SAK-TC1767-256F80HL AD
• Description: IC MCU 32BIT FLASH 176-LQFP
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1767-256F80HL AD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 88
• Program Memory Size: 2MB (2M x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 4x10b, 32x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 176-LFQFP
• Data Bus Width: 32 bit
• Data Ram Size: 92 KB
• Interface Type: SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (12 bit, 16 Channel)
• Packages: PG-LQFP-176
• Max Clock Frequency: 80.0 MHz
• Sram (incl. Cache): 128.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 2.0 MB
• For Use With: B158-H8539-G2-X-7600IN - KIT STARTER TC176X SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SP000442086

2.4.7.2
General Features
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Figure 13
As shown in
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Data Sheet
Extreme fast conversion, 21 cycles of
10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
Successive approximation conversion method
Each differential input channel can also be used as single-ended input
Offset calibration support for each channel
Programmable gain of 1, 2, 4, or 8 for each channel
Free-running (Channel Timers) or triggered conversion modes
Trigger and gating control for external signals
Built-in Channel Timers for internal triggering
Channel timer request periods independently selectable for each channel
Selectable, programmable digital anti-aliasing and data reduction filter block with four
independent filter units
An Input Structure containing the differential inputs and impedance control.
Interrupt
GS[H:A]
TS[H:A]
Control
Control
Clock
DMA
FADC Short Description
Figure
Block Diagram of the FADC Module with 4 Input Channels
f
f
FADC
CLC
SRx
SRx
13, the main FADC functional blocks are:
V
FAREF
Control
V
FAGND
A/D
Channel
Trigger
Control
V
DDAF
V
SSAF
Reduction
Converter
f
Stage
FADC
47
Data
V
Unit
A/D
DDMF
Channel
V
Timers
clock (262.5 ns @
SSMF
V
DDIF
FAIN0P
FAIN0N
FAIN1P
FAIN1N
FAIN2P
FAIN2N
FAIN3P
FAIN3N
f
FADC
input
channel 0
input
channel 1
input
channel 2
input
channel 3
= 80 MHz)
MCB06065_m4
Introduction
V1.3, 2009-09
TC1767