AT91R40807-33AI Atmel, AT91R40807-33AI Datasheet - Page 103

• Manufacturer Part Number: AT91R40807-33AI
• Description: IC ARM7 MCU 176 TQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91R40807-33AI

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Transmitter
Time-guard
Multi-drop Mode
1354D–ATARM–08/02
The transmitter has the same behavior in both synchronous and asynchronous operat-
ing modes. Start bit, data bits, parity bit and stop bits are serially shifted, lowest
significant bit first, on the falling edge of the serial clock. See example in Figure 41.
The number of data bits is selected in the CHRL field in US_MR.
The parity bit is set according to the PAR field in US_MR.
The number of stop bits is selected in the NBSTOP field in US_MR.
When a character is written to US_THR (Transmit Holding), it is transferred to the Shift
Register as soon as it is empty. When the transfer occurs, the TXRDY bit in US_CSR is
set until a new character is written to US_THR. If Transmit Shift Register and US_THR
are both empty, the TXEMPTY bit in US_CSR is set.
The Time-guard function allows the transmitter to insert an idle state on the TXD line
between two characters. The duration of the idle state is programmed in US_TTGR
(Transmitter Time-guard). When this register is set to zero, no time-guard is generated.
Otherwise, the transmitter holds a high level on TXD after each transmitted byte during
the number of bit periods programmed in US_TTGR
When the field PAR in US_MR equals 11X (binary value), the USART is configured to
run in Multi-drop Mode. In this case, the parity error bit PARE in US_CSR is set when
data is detected with a parity bit set to identify an address byte. PARE is cleared with the
Reset Status Bits Command (RSTSTA) in US_CR. If the parity bit is detected low, iden-
tifying a data byte, PARE is not set.
The transmitter sends an address byte (parity bit set) when a Send Address Command
(SENDA) is written to US_CR. In this case, the next byte written to US_THR will be
transmitted as an address. After this any byte transmitted will have the parity bit cleared.
Figure 41. Synchronous and Asynchronous Modes: Character Transmission
Baud Rate
Example: 8-bit, parity enabled 1 stop
Clock
TXD
Start
between two characters
Bit
Idle state duration
D0
D1
D2
=
D3
Time-guard
D4
Value
D5
AT91X40 Series
x
D6
Period
Bit
D7
Parity
Bit
Stop
Bit
103