AT91R40807-33AI Atmel, AT91R40807-33AI Datasheet - Page 9

• Manufacturer Part Number: AT91R40807-33AI
• Description: IC ARM7 MCU 176 TQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91R40807-33AI

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

JTAG/ICE Debug
Memory Controller
Internal Memories
Using Internal Memories
1354D–ATARM–08/02
To enter tri-state mode, the pin NTRI must be held low during the last 10 clock cycles
before the rising edge of NRST. For normal operation, the pin NTRI must be held high
during reset, by a resistor of up to 400K Ohm.
NTRI is multiplexed with I/O line P21 and USART 1 serial data transmit line TXD1.
Standard RS-232 drivers generally contain internal 400K Ohm pull-up resistors. If TXD1
is connected to a device not including this pull-up, the user must make sure that a high
level is tied on NTRI while NRST is asserted.
ARM standard embedded In-circuit Emulation is supported via the JTAG/ICE port. The
pins TDI, TDO, TCK and TMS are dedicated to this debug function and can be con-
nected to a host computer via the external ICE interface.
In ICE Debug Mode, the ARM7TDMI core responds with a non-JTAG chip ID that identi-
fies the microcontroller. This is not fully IEEE1149.1 compliant.
The ARM7TDMI processor address space is 4G bytes. The memory controller decodes
the internal 32-bit address bus and defines three address spaces:
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•
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In any of these address spaces, the ARM7TDMI operates in Little-Endian Mode only.
The AT91X40 Series Microcontrollers integrate one or two banks of internal static
SRAM and/or one bank of ROM. All internal memories are 32 bits wide and single-clock
cycle accessible. Byte (8-bit), halfword (16-bit) or word (32-bit) accesses are supported
and are executed within one cycle. Fetching Thumb or ARM instructions is supported
and internal memory can store twice as many Thumb instructions as ARM ones.
All the AT91X40 Series Microcontrollers integrate a primary 8-Kbyte or 256-Kbyte
SRAM bank, accessible at address 0x0 (after the remap).
The AT91R40807 integrates a secondary SRAM memory bank of 128K bytes at
address 0x10 0000. This secondary bank can be used to emulate the ROM of the
AT91M40807.
The AT91M40807 Microcontroller integrates 128K bytes of internal ROM at address
0x10 0000. It offers a reduced-cost option of the AT91R40807 for high-volume applica-
tions in which the software is stable.
The primary RAM bank is always mapped at address 0x30 0000 before remap and at
address 0x0 after the remap, allowing ARM7TDMI exception vectors to be modified by
the software. Making the RAM bank accessible before remap allows the user to copy
ARM exception vectors and boot code into the bank prior to remap.
The rest of the bank can be used for stack allocation to speed up context saving and
restoration, or as data and program storage for critical algorithms.
Placing the SRAM on-chip and using a 32-bit data bus bandwidth maximizes microcon-
troller performance while minimizing system power consumption. The 32-bit bus
optimizes use of the ARM instruction set and offers the ability to process data wider than
16 bits, thus making optimal use of the ARM7TDMI advanced performance.
The capability to update application software dynamically in an internal SRAM bank
adds an extra dimension to the AT91X40 Series Microcontrollers.
Internal Memories in the four lowest megabytes
Middle Space reserved for the external devices (memory or peripherals) controlled
by the EBI
Internal Peripherals in the four highest megabytes
AT91X40 Series
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