AT91R40807-33AI Atmel, AT91R40807-33AI Datasheet - Page 71

• Manufacturer Part Number: AT91R40807-33AI
• Description: IC ARM7 MCU 176 TQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91R40807-33AI

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Standard Interrupt
Sequence
1354D–ATARM–08/02
It is assumed that:
•
•
When NIRQ is asserted, if the bit I of CPSR is 0, the sequence is:
1. The CPSR is stored in SPSR_irq, the current value of the Program Counter is
2. The ARM core enters IRQ Mode, if it is not already.
3. When the instruction loaded at address 0x18 is executed, the Program Counter
4. The previous step has effect to branch to the corresponding interrupt service
5. Further interrupts can then be unmasked by clearing the I bit in the CPSR, allow-
6. The Interrupt Handler can then proceed as required, saving the registers which
7. The I bit in the CPSR must be set in order to mask interrupts before exiting, to
8. The End Of Interrupt Command Register (AIC_EOICR) must be written in order
9. The SPSR (SPSR_irq) is restored. Finally, the saved value of the Link Register is
The Advanced Interrupt Controller has been programmed, AIC_SVR are loaded
with corresponding interrupt service routine addresses and interrupts are enabled.
The Instruction at address 0x18(IRQ exception vector address) is
ldr pc, [pc, # - &F20]
loaded in the IRQ link register (r14_irq) and the Program Counter (r15) is loaded
with 0x18. In the following cycle during fetch at address 0x1C, the ARM core
adjusts r14_irq, decrementing it by 4.
is loaded with the value read in AIC_IVR. Reading the AIC_IVR has the following
effects:
–
–
–
–
–
routine. This should start by saving the Link Register(r14_irq) and the
SPSR(SPSR_irq). Note that the Link Register must be decremented by 4 when it
is saved, if it is to be restored directly into the Program Counter at the end of the
interrupt.
ing re-assertion of the NIRQ to be taken into account by the core. This can occur
if an interrupt with a higher priority than the current one occurs.
will be used and restoring them at the end. During this phase, an interrupt of pri-
ority higher than the current level will restart the sequence from step 1. Note that
if the interrupt is programmed to be level sensitive, the source of the interrupt
must be cleared during this phase.
ensure that the interrupt is completed in an orderly manner.
to indicate to the AIC that the current interrupt is finished. This causes the cur-
rent level to be popped from the stack, restoring the previous current level if one
exists on the stack. If another interrupt is pending, with lower or equal priority
than old current level but with higher priority than the new current level, the NIRQ
line is re-asserted, but the interrupt sequence does not immediately start
because the I bit is set in the core.
restored directly into the PC. This has effect of returning from the interrupt to
whatever was being executed before, and of loading the CPSR with the stored
Set the current interrupt to be the pending one with the highest priority. The
current level is the priority level of the current interrupt.
De-assert the NIRQ line on the processor. (Even if vectoring is not used,
AIC_IVR must be read in order to de-assert NIRQ)
Automatically clear the interrupt, if it has been programmed to be edge
triggered
Push the current level on to the stack
Return the value written in the AIC_SVR corresponding to the current
interrupt
AT91X40 Series
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